DDR5, not LPDDR5, in M5??

[NotEntirelyConfused]

EE Times Japan claims that Apple's using DDR5, not LPDDR5, in at least the M5 Pro and Max versions.

This seems about as likely as the sun rising in the west. It would require a reimplementation of the memory controller, but worse, it would blow the power budget for the chip by a ridiculous factor.

Is there something I'm missing about this, or is this just the usual case of a tech reporter having no clue what they're talking about?

 

[casperes1996]

U have no evidence but I would find that quite unlikely honestly.

 

[mr_roboto]

I saw the same thing, and I'm not sure how much I trust that article's author to provide informed analysis.

Maybe something's being lost in translation, but there's at least one idea that seemed quite wrongheaded to me: they think improved tech has enabled Apple (and some Apple competitors) to spend transistors freely on all-big-cores CPU configurations. But die photos are out there, and they show that an M5 Pro big core occupies about twice as much floorplan as the mid core. (I am measuring the area of the core + its private caches, and excluding the shared structures in the respective clusters.)

So, M5 P/M are not assemblies of nothing but big cores. The closest Apple's ever come to that was M4 Pro and Max, with their two P clusters containing six big cores each, and a 4-core E cluster (cut down from 6 E cores in base M4).

 

[Cmaier]

I don’t believe it

 

[dada_dave]

I saw the same thing, and I'm not sure how much I trust that article's author to provide informed analysis.

Maybe something's being lost in translation, but there's at least one idea that seemed quite wrongheaded to me: they think improved tech has enabled Apple (and some Apple competitors) to spend transistors freely on all-big-cores CPU configurations. But die photos are out there, and they show that an M5 Pro big core occupies about twice as much floorplan as the mid core. (I am measuring the area of the core + its private caches, and excluding the shared structures in the respective clusters.)

So, M5 P/M are not assemblies of nothing but big cores. The closest Apple's ever come to that was M4 Pro and Max, with their two P clusters containing six big cores each, and a 4-core E cluster (cut down from 6 E cores in base M4).

Oh the die shots are out? I’ve been kind of out of the loop recently - Edit: two months ago? I really have been out of the loop.

 

[NotEntirelyConfused]

Yeah the all-big-cores idea seems dubious at best but it's really the power budget issue that seems to make the claim utterly impossible. And not by a small margin, either.

 

[leman]

Extraordinary claims require extraordinary evidence. Until that has been provided, LPDDR it is

 

[NotEntirelyConfused]

Extraordinary claims require extraordinary evidence. Until that has been provided, LPDDR it is

Amusing, I think it was you who said the same thing about the use of LPDDR6. You weren't wrong...