TSMC 3nm FinFlex technology

[Cmaier]

Announced today, looks like:

TSMC FINFLEX™ – Ultimate Performance, Power Efficiency, Density and Flexibility - Taiwan Semiconductor Manufacturing Company Limited

Many product designs are a series of compromises. Take for example, electric vehicles, wouldn’t it be great to have a 1000-mile or 1600-kilometer range in an EV? But consider what compromises would need to be made to achieve this goal. The battery would be massive and heavy, leading to an...

www.tsmc.com

To me, this is fairly foreign. I predated the actual use of finfets, so we were always able to craft our own transistors (just by crossing a polysilicon over an arbitrarily shaped active region). Not sure whether or not non-foundry fabs (i.e. Intel) limit to pre-formed transistors like this. Right now, presumably, designers who need, say, something like a 2-2 FET would combine two 1-2 FETs, or whatever. (The first digit is the number of gates, the second is the number of fins per gate).

It would be a very interesting EDA problem to figure out how to select each transistor, though presumably Apple mostly uses a cell library and just performs swaps of low, medium, or high power cells as necessary. Given the number of circuit designers they have working there, i assume they design their own macrocells for things like static RAM, but who knows.

 

[theorist9]

More details on this from Anton Shilov at Anandtech:

TSMC Readies Five 3nm Process Technologies, Adds FinFlex For Design Flexibility

www.anandtech.com

It seems this could allow Apple to have a future N3-based Mx for the Air that favors efficiency, and a future N3-based Mx Ultra for the Studio that favors performance (and likewise for the extreme chip in the Mac Pro) (where x=3, probably). But I don't know if Apple wants to invest the design effort to have different core designs in different levels of Mx's. It is interesting that, regardless of whether they do that, they can mix and match these within a chip to tailor certain parts for performance and certain parts for efficiency, e.g., use the 3-2 in one area, the 2-2 in another, etc.

 

[Cmaier]

More details on this from Anton Shilov at Anandtech:

TSMC Readies Five 3nm Process Technologies, Adds FinFlex For Design Flexibility

www.anandtech.com

It seems this could allow Apple to have a future N3-based Mx for the Air favors efficiency, and one for the N3-based Mx Ultra that favors performance. But I don't know if Apple wants to invest the design effort to have different P and E cores in different Mx's. It is interesting that, regardless of whether they do that, they can mix and match these within a chip to tailor certain parts for performance and certain parts for efficiency. they'll instead keep the scheme they have now, where all levels of chips have the same P and E cores, use this to do tailoring within the chip, e.g., use the 3-2 in one area, the 2-2 in another, etc.

Yeah, i seriously doubt they would have different physical designs like that. I don’t even think it would be a P-core vs. E-core thing. The way I read this, it’s more likely to be used on a critical path vs. critical path situation.

When I was at exponential, designing powerpc’s, we had an EDA tool called Hoover. The idea behind it was it would figure out whether to use the high, medium, or low power version of each gate in the design, depending on the timing requirements of the paths through the gate.
It was something designers were supposed to do by hand, anyway, but the idea was that this would be more reliable, and would be much faster to do each time someone had to change the logic for other reasons. Turns out that hoover broke the chip - it ran much slower than it was supposed to. We failed to account for the fact that smaller gate currents meant that there would be more cross-coupling speed degradation between some of the wires.

Anyway…. When I was designing in CMOS for x86 or SPARC, we would size each transistor in a gate, by drawing arbitrary transistor gate shapes/sizes and arbitrary active region shapes/sizes - the only limitation was the design rules about spacing, minimum dimensions, and minimum shape areas and the like. But apparently the FINFETs, unlike MOSFETs, are available only in quantized configurations. The way I read TSMC’s website is that this lets you mix and match those configurations within a chip - which I was surprised you couldn’t do before. So this should allow more efficient designs, because you can do things like set the critical path through the adder to use 3-2, but set a random control signal in the same core to use 1-1. I haven’t seen the design rules, but it *seems* like you don’t need to, say, make the entire P-core be one type of transistor and the entire E-core be another.