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From what I understand the  idea of the patent is combining multiple dies in a 2.5D configuration in a way that’s compact and cost-efficient. They explicitly mention the possibility of manufacturing two dies on different node, e.g the logic die on a more advanced node and the cache/IO die on an older node (since it wouldn’t scale very well with node size). This would be a very good way IMO to solve their issues with compute density and die cost.