Yeah, I have questions here. My experience was difference, because we always designed our own cell libraries. And, for a given gate, we had many variations, with different power levels and, sometimes, alternate layouts.
So, for example, we had a NAND2x1, NAND2x2, NAND2x4, etc. We might even have a NAND2x4a or whatever, if, for some reason, somebody needed an alternate version of NAND2x4 with a different layout.
The “x” number was the relative width-to-length ratio of the cell as compared to x1. So NAND2x2 had double the strength as NAND2x1. Of course, with FINFETS, you are looking at number of fins (or whatever terminology different companies use) and not W/L ratio.
What we would do is size the gates as optimally as we could, choosing x4’s or x8’s when necessary to make timing on some important path, and using x1’s where we could get away with it.
All of which is to say, we could mix and match high-density and high performance gates.
What I think is going on with TSMC’s libraries, though, is something different.(I have no access to their cell libraries, so my guess could be wrong). What i think is going on is the HD and HP cells use different “standard cell architectures,“ which means you can’t mix and match them. By “standard cell architecture”I refer to the cell height and location of the power rails. The cell is a rectangle, with a horizontal metal layer on the top and another on the bottom, one for power and one for ground. These line up with neighboring cells, so you distribute power and ground just by abutting them. But if a HD inverter has a different cell height than a HP inverter, then you can’t do that.
We did something like that at Exponential. Our “datapath” cells were actually designed to have constant width but variable height, so that each bit of a datapath formed a uniform column. Our “control” cells were constant height and variable width, which is what everyone in CMOS does.
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