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yeah, that was my recollection.

actually, putting my brain hat on, I don’t see how it would even help a RAM very much.  I admit I’m not much of an expert on FINFET cell designs, so maybe that changes things from MOSFETS (though I doubt it).  But right now what you would likely do is route power and ground rails horizontally over the top of the RAM cells (at the top and bottom of the cell), and touch down vias to where you need contacts. Routing the rails on the backside, instead, frees up a couple horizontal routing channels, sure (but I assume those must require pretty massive vias to tunnel through the die. I am not sure. Those could block routing channels). I don’t think RAMs are generally constrained by the number of available horizontal routing tracks, but let’s say they are.  Backside, if it frees up some tracks, frees up maybe a few.  Say 4.  So you can add a couple read/write ports by freeing them up, maybe. 

On the other hand, those power/ground rails were useful for other reasons - you can use them as shields around the data wires - those all switch at once, and can cause cross-coupling unless you shield them, or increase their spacing or swizzle them.