Ubuntu ISA upgrade - moving RISC V to RVA 23

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tomO2013

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I've been thoroughly enjoying the canonical talks on YouTube.

This talk was particularly interesting to me focusing on RISCV and achieving parity with ARMv9 ISA.



I figured that some of you guys here might find it enjoyable (whether or not you'd agree with the thoughts being shared).

I guess it makes sense for Ubuntu and Debian to leave rv64gc behind and move to a baseline of RVA23 for future LTS releases (with mandatory cryptographic, vector and hypervisor extensions).

Anyway, hope y'all enjoy.
 
Thank you for this, will check it out once I have stable internet and some time. Quite puzzlingly, I was not able to find clear information of what’s actually contained in RvA23, aside the very vague “vector” mention. Do you know whether there is a list of features I can find somewhere?
 
Hi @leman,

I had similar questions which lead me down a rabbit hole watching this ...


I find it all very interesting, especially his throwaway comments about having broad compiler support today.

Hope it answers some of the questions that you might have.
 
Thanks! I’d hoped there would be a written document somewhere. Due to work, travel, and family constraints it’s unlikely I’d be able to watch these videos in the next few days. As far as I know there are multiple versions of the vector extension and it would be interesting to know which one ended up to be in the profile.
 
My pleasure :)
There is some interesting documentation on the RISCV website and github - it's nice to see specifications openly being published :)

RISC-V Technical Specifications - Home - RISC-V Tech Hub

riscv.atlassian.net riscv.atlassian.net

github.com

RISC-V

The Open-Standard Instruction Set Architecture. RISC-V has 64 repositories available. Follow their code on GitHub.
github.com github.com

This is an interesting (if a little lightweight) essay on parameterized vector width support in RISCV whereby vector registers can have variable length instead of predetermined width.



and here is a simple write up on opencv.org evidencing performance improvements with the introduction of RVV
opencv.org

Introducing HAL riscv-rvv: Unleashing the power of RISC-V CPUs with RVV 1.0

This article was written by Yuantao Feng of the OpenCV China Team. What is RISC-V and RVV 1.0? RISC-V (pronounced “risk-five”) is an open standard instruction set architecture (ISA) based on the principles of reduced instruction set computing (RISC). Unlike proprietary ISAs such as Intel’s x86...
opencv.org opencv.org

My understanding is that SiFive (the video I linked to earlier is from one of their architects) has one of the more mature implementations of RVV in the market with X280 and X300 series IP. X300 IP in particular is used as part of their XM offering where 4 X300 gen2 cores are paired with a large matrix engine for inference workloads).

 
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