A nice article on ISAs and microarchitectures

[Cmaier]

Given that their E-cores are fairly compact, and also quite capable, it seems like it might not be that difficult. Construct FutuArch, which will have a streamlined decode scheme and slightly different behavior patterns, and put it into FP-cores and FE-cores while still retaining 4 or 6 xE-cores to support legacy code. Five years down the road, the chip will be down to 2 xE-cores and may never be able to get past having one in there, but all the important software will have been rebuilt for or translated to FutuArch, which will be a tremendous efficiency gain over x86-64.

The last time Intel came up with a new easy-to-decode ISA it didn’t turn out so well for them

 

[Yoused]

The last time Intel came up with a new easy-to-decode ISA it didn’t turn out so well for them

It is conceivable that VLIW could be done well. After all, Transmeta had a sort of decent product that showed good efficiency. But everyone called the Intel product "Itanic", and they never put any effort into trying to improve the μarch or otherwise refine it. And Intel is the only mainstream company that still uses byte-based coding. They do it well, but it is a bit like building jet airplanes with straight wings, which basically nobody does.

 

[dada_dave]

It is conceivable that VLIW could be done well. After all, Transmeta had a sort of decent product that showed good efficiency. But everyone called the Intel product "Itanic", and they never put any effort into trying to improve the μarch or otherwise refine it. And Intel is the only mainstream company that still uses byte-based coding. They do it well, but it is a bit like building jet airplanes with straight wings, which basically nobody does.

Aye, even back on the day VLIW had a few good uses like scientific compute (I believe I mentioned on here before that my Dad had a couple of Itaniums and loved them, though he loved the prior Deck Alphas more) and as the article mentioned early GPUs. That said, it would be a tall order to introduce a new architecture, especially one so different as VLIW. The best bet would be for a new market for which that architecture was ideally suited and then build up a base around that then onward and upward - just like ARM did.

 

[Cmaier]

Aye, even back on the day VLIW had a few good uses like scientific compute (I believe I mentioned on here before that my Dad had a couple of Itaniums and loved them, though he loved the prior Deck Alphas more) and as the article mentioned early GPUs. That said, it would be a tall order to introduce a new architecture, especially one so different as VLIW. The best bet would be for a new market for which that architecture was ideally suited and then build up a base around that then onward and upward - just like ARM did.

Alpha kicked ass. Most of the guys I worked with on the circuit design team at AMD were former DEC Alpha designers. They designed those whole chips at the circuit schematic level - it was wild. You need a nand gate? You draw a schematic for a nand gate and you lay out a nand gate. Great for clock speed, but impossible to manage if you wanted to do complex microarchitectures to raise IPC. Loved those guys - a couple of them were hilarious.

 

[Citysnaps]

They designed those whole chips at the circuit schematic level - it was wild. You need a nand gate? You draw a schematic for a nand gate and you lay out a nand gate.

That's the way our communications-oriented signal processing ASIC startup (Graychip, in Palo Alto) designed chips. Schematic entry -> our own simulator -> hand laid out via UCB's Magic -> and zebra fabbed by ES2 in Aix-en-Provence, France (ES2 later being acquired by Atmel).

Our competitors couldn't get close to our speed/performance, low power consumption, and functionality.

 

[Cmaier]

That's the way our communications-oriented signal processing ASIC startup (Graychip, in Palo Alto) designed chips. Schematic entry -> our own simulator -> hand laid out via UCB's Magic -> and zebra fabbed by ES2 in Aix-en-Provence, France (ES2 later being acquired by Atmel).

Our competitors couldn't get close to our speed/performance, low power consumption, and functionality.

Works great when your design is small. But try designing a CPU with a billion transistors that way

 

[dada_dave]

Works great when your design is small. But try designing a CPU with a billion transistors that way

AI will solve it! (Only half joking, this is the sort of thing AI actually can be good at)

 

[Citysnaps]

Works great when your design is small. But try designing a CPU with a billion transistors that way

For sure on that. We knew where our lane was and intentionally only addressed communications-oriented signal processing using digital techniques. And kept the company very small so that the founders and employees could keep normal (or less, as needed) hours and have time for their kids. Everybody had a hand-me-down SPARCStation 1 or 2, which worked fine for our needs (except I really hated vi coming from the Mac world). The company was run very low key, with zero drama - and loads of time off if you needed it to tend to personal matters (sick spouse, a pet on its last legs, etc).

Our margins were high because there was no competition and we could get away with it - though that was really driven by customers in the early stages of a project often needing a lot of hand-holding not knowing a lot about digital domain signal processing. A chip that cost us around $20-$30 through package and test we'd sell for $300 in small quantities.

Out of the three professional jobs over my career, that one was the most satisfying.