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From what I understand, the primary motivation for VLIW was to explicitly schedule parallel execution units. That is, if your processor has three parallel pipelines, your instruction will encode three instructions to be executed by these pipelines in parallel — as opposed to other superscalar architectures that do scheduling dynamically. In a classical VLIW there is therefore a tight coupling between the instruction format and the number of execution units.

I am not too familiar with IA-64 architecture, if I remember correctly they introduced features that would enable additional scalability. This allowed the CPU to execute multiple VLIW instructions in parallel using the scheduling information provided by the instructions. This allowed Itanium to surpass the limitation of VLIW and offer a wider execution backend than a single instruction can  encode.