Core Memory – in the 21st century? (STT-MRAM)

Yoused

up
Posts
5,987
Reaction score
9,721
Location
knee deep in the road apples of the 4 horsemen
I have been reading a bit about Spin Transfer Torque memory, and it seems intriguing. The advantages look too appealing to ignore.

At present, one company, Everspin, has a 1Gb chip available, which suggests to me that this tech may be starting to crest the horizon.

Like old-fashioned core memory from the '60s, STT-RAM holds data in magnetic domains (nano-tracts of paired chip real estate, rather than tiny magnets woven into a wire grid) and is non-volatile. Unlike core, it is not read-destructive (though the read/write flux difference is disturbingly tight).

The large chip runs at two-thirds of a GHz, so it is a tad slow compared to DRAM (DDR3, AIUI). At that speed, it looks barely usable – unless significant alterations are made to L3 cache protocols and/or memory hierarchy layout (e.g., some kind of sectoring scheme that allow a large block of L3 to be used as a unit, such as for a stack).

But, for a phone, STT-RAM looks eminently worthwhile. Saving the DRAM-refresh penalty could bring us back to phones you need to charge weekly rather than daily.

When it arrives in tablet and notebook devices, it is likely that battery life will, again, be counted in days rather than hours. And "Off" will basically mean what "Sleep" does now (you will literally have to do a purge-reboot operation to fix some issues). And while it may seem kind of pointless for a desktop, we do occasionally have power outages, which would amount to but a blink in one's workflow, rather than a restart (lost work) or UPS box alarm.

What are the concerns? I am not clear on this, but if portable devices are moving toward induction charging, magnetic domain memory damn well better be properly shielded – but, we had magnetic surface HDs for decades without major field interference issues. What about security? If it is NVRAM, your transient data is not wiped with a shutdown, so the OS better be designed to properly clean memory as needed (or use sectored-L3-only for sensitive transient data).

And of course there is price. These chips will start out as more expensive than DRAM, so the improved new devices using it will cost more. I am betting that many of us will be clamoring for the new stuff.
 

leman

Site Champ
Posts
733
Reaction score
1,400
I would like to see this technology in smartwatches. The need to charge practically every day is really annoying.
 

theorist9

Site Champ
Posts
671
Reaction score
639
When it arrives in tablet and notebook devices, it is likely that battery life will, again, be counted in days rather than hours.
I thought RAM energy usage was only a small percentage of that of the device as a whole, and that most is consumed by the display, CPU, and GPU. So I don't understand how reducing (or even eliminating) the RAM power draw could so significantly change battery life.
 
Last edited:

Cmaier

Site Master
Staff Member
Site Donor
Posts
5,666
Reaction score
9,312
I thought RAM energy usage was only a small percentage of that used by the device as a whole, and that most is consumed by the display, CPU, and GPU. So I don't understand how reducing (or even eliminating) the RAM power draw could so significantly change battery life.
Rule of thumb, I’d say DRAM is <10% of power draw.
 

Citysnaps

Elite Member
Staff Member
Site Donor
Posts
4,029
Reaction score
9,705
Main Camera
iPhone
Just idle curiosity... I wonder if their tech is intrinsically radiation-hardened? That could be useful for space applications, where external shielding for non-hardened chips implies a cost/penalty.
 

theorist9

Site Champ
Posts
671
Reaction score
639
Just idle curiosity... I wonder if their tech is intrinsically radiation-hardened? That could be useful for space applications, where external shielding for non-hardened chips implies a cost/penalty.
Interesting question. AFAIK, NASA and others are still using the radiation-hardened RAD750 CPU for their most extreme applications (it was included in the Webb), which is made on either a 150 nm or 250 nm process—and costs ~$300k/unit! [$500k if you include the wheels.]

They stick with it because they know it works, and its ~300 MIPS is sufficient for their rather modest local processing requirements. The large feature size is a benefit, since it reduces the ability of radiation to disrupt or damage the processor. I assume they have something similar for RAM.

But eventually they will need to upgrade, at which point this tech might be interesting if it is indeed more robust against radiation than conventional RAM.

 
Last edited:

Cmaier

Site Master
Staff Member
Site Donor
Posts
5,666
Reaction score
9,312
Just idle curiosity... I wonder if their tech is intrinsically radiation-hardened? That could be useful for space applications, where external shielding for non-hardened chips implies a cost/penalty.

I designed a rad hard CPU one time. Key was to use a semiconductor without a direct bandgap, so that you can’t promote a charge carrier just by increasing energy - you also need to affect angular momentum (and hit the right quantum). GaAs or InP are good choices.
 

Cmaier

Site Master
Staff Member
Site Donor
Posts
5,666
Reaction score
9,312
I designed a rad hard CPU one time. Key was to use a semiconductor without a direct bandgap, so that you can’t promote a charge carrier just by increasing energy - you also need to affect angular momentum (and hit the right quantum). GaAs or InP are good choices.

I forgot the other key. Full differential logic. Evey signal is carried on a pair of wires that run alongside each other. One wire is a 0 and the other a 1. “True” or “false” are determined based on which wire has the 1 at any given time. If a stray alpha particle comes along and injects charge into one of the wires, it will also inject a similar amount of charge into the other. Both wires will change their voltage by about the same amount. The difference in voltage between the wires remains the same, and that’s all that matters to the downstream circuits. That also means that every RAM cell stores both the value and its logical complement, in a symmetric structure, and every logic gate switches in both directions at once. This keeps the total current nice and smooth, which also helps defeat differential power analysis sidechannel attacks.
 

Cmaier

Site Master
Staff Member
Site Donor
Posts
5,666
Reaction score
9,312
Basically, CMOS?
No! CMOS is single-ended. Every gate pulls its output either up or down. In CMOS you have inverter cells because you need them. In differential logic you don’t need inverters - you just cross the two output wires. For example, a differential AND gate has two outputs: Z and Z!. The outputs always have opposite values. If Z is a 1, then the output is “true.” And each input is also differential - A, A!, B, B!, etc.

Instead of turning current on and off, like you do with CMOS gates, you steer the current through one of two identical paths through the gate. Depending on which path you take, you raise or lower each output. This means there is no such concept as “dynamic power.” There’s only static power (but static power is high, unlike CMOS).

Since every wire now has two versions, we rigged up a tool to take a single “fat” wire and split it down the middle. If we needed an inverter, we essentially just flipped the wires when they turned a right-angle corner. Turns out that you can mathematically prove there are something like 8 possible configurations that you can recognize and use to cut the wires. Lt. Col. James T. Loy, a Westpoint professor who I went to grad school with, figured it all out.

At Exponential we did something similar, but only for datapaths. Random control logic was single-ended.
 

Citysnaps

Elite Member
Staff Member
Site Donor
Posts
4,029
Reaction score
9,705
Main Camera
iPhone
Interesting question. AFAIK, NASA and others are still using the radiation-hardened RAD750 CPU for their most extreme applications (it was included in the Webb), which is made on either a 150 nm or 250 nm process—and costs ~$300k/unit! [$500k if you include the wheels.]

My company focused on a small line of CMOS digital signal processing ASICs (digital down/up converters, digital filters, digital QAM modulators/demodulators, etc). Over the years we got a couple inquiries about making special rad-hardened versions of our chips for govt. space programs; something we had zero experience with. Those customers wanted our chips, but we couldn't convince them to consider shielding (more weight and gas for thrusters). The only viable option was to partner with someone like TRW (now Northrup-Grumman) or Harris Semiconductor (a competitor - nope) for rad-hardened chips. In the end we decided to pass - a smart move as it would have sucked a lot of $$$ and been a huge distraction, and also very risky.
 
Top Bottom
1 2