Intel supposedly going to fab Apple chips

Cmaier

Cmaier

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I know, I saw it come across the APPL stock news wire, and the article tagline made it sound like Apple was switching back to Intel. It had me confused for about a minute.
 
Yoused said:
TSMC has at least 1 fab in the US. I think it is up and running.
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sounds like TSMC is insisting it will always be at least a node behind, because Americans are too dumb and lazy to push buttons properly.
 
My question would be, you cannot just take masks for one process, transfer them to a different process and get comparable results, right? How much work is it to rework the layout for optimal performance?
 
Correct, you cannot do that. And it wouldn't be a matter of suboptimal performance, it just wouldn't work at all.

In the distant past you might have been able to use masks in different fabs as-is, but back then things were a lot more standardized. Today, nobody builds transistors the same way, everyone uses slightly different materials, everyone has different design rules, everyone has different feature size limits, and on and on.

You need to re-do the whole physical design to retarget a chip for a different fab. Even the basic floorplan layout (where blocks sit relative to each other) might not survive. You also need different PLLs, SRAMs, and many other things.
 
mr_roboto said:
Correct, you cannot do that. And it wouldn't be a matter of suboptimal performance, it just wouldn't work at all.

In the distant past you might have been able to use masks in different fabs as-is, but back then things were a lot more standardized. Today, nobody builds transistors the same way, everyone uses slightly different materials, everyone has different design rules, everyone has different feature size limits, and on and on.

You need to re-do the whole physical design to retarget a chip for a different fab. Even the basic floorplan layout (where blocks sit relative to each other) might not survive. You also need different PLLs, SRAMs, and many other things.
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I wonder how much they automate stuff there. Most of my career I was a physical designer, so my entire job was creating a netlist and cell placement by hand by reading an RTL description, prerouting key buses and signals by hand, and then corralling the router to finish the job. This took up the majority of the project timeline. Obviously they rely a lot more on synthesis than we did, and they aren’t creating their own standard cells like we were, but it still seems like a very time-consuming amount of work, even if Intel hands them PLL, SRAM and driver macros, etc.

We once did a design that was intended to be fab-able by two different foundries, but the foundries were pretty close in terms of their design rules, and we were able to come up with a least-common-denominator set of rules that allowed it to work. Can’t see how you could do that sort of thing with FINFETs, though, unless Intel has gone out of its way to provide a cell library that is 1:1 to TSMC’s.
 
Cmaier said:
Can’t see how you could do that sort of thing with FINFETs, though
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TSMC N2 is GAAFET, and so is Intel 18A as I recall, so the rules you were familiar with have changed somewhat. Even the FinFlex/GAAFlex layouts might be problematic for a stone-knives-and-bearskins fogey like you, at least at first.
 
Yoused said:
TSMC N2 is GAAFET, and so is Intel 18A as I recall, so the rules you were familiar with have changed somewhat. Even the FinFlex/GAAFlex layouts might be problematic for a stone-knives-and-bearskins fogey like you, at least at first.W
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When i say finfet, I mean all the stuff that came after MOSFETs. These all require pre-formed transistors, unlike MOSFETs where you can literally draw poly over active in a CAD tool and create any shape transistor you want.
 
One thing has always confused me: in those illustrations, does the gate block form a lead barrier? Because I always visualize the leads as continuos through the gate.
 
Yoused said:
One thing has always confused me: in those illustrations, does the gate block form a lead barrier? Because I always visualize the leads as continuos through the gate.
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I am not sure I understand the question. What do you mean by “lead?” Are you referring to the source/drain structure? (which I would call the “channel”). If so, that structure extends through the gate - the gate surrounds it, like a blood pressure cuff on your arm (and the principal of operation isn’t all too different, really).

By supplying a charge of one polarity on the gate, a charge of the opposite polarity tends to form in the surfaces of the channel near the gate surface. If the induced charge is of the correct polarity, this allows current to flow from drain to source. If not, it prevents (mostly) charge from flowing.
 
Cmaier said:
By supplying a charge of one polarity on the gate, a charge of the opposite polarity tends to form in the surfaces of the channel near the gate surface. If the induced charge is of the correct polarity, this allows current to flow from drain to source. If not, it prevents (mostly) charge from flowing.
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OK, that makes sense. I guess one of the sources of my confusion is that they show the gate structure but never seem to depict the current supply line that regulates the gate's polarity.
 
Yoused said:
OK, that makes sense. I guess one of the sources of my confusion is that they show the gate structure but never seem to depict the current supply line that regulates the gate's polarity.
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yeah, they don’t usually show these things wired up. One thing to remember is the fin (the structure including the source, drain, and channel between them) is silicon (doped with P or B, depending on whether it’s a n- or p- channel). The gate is some form of SiO2 (i.e. glass). Metal or heavily doped polysilicon connects to the gate, the source, and the drain and is used to wire the transistors together.
 
Cmaier said:
yeah, they don’t usually show these things wired up. One thing to remember is the fin (the structure including the source, drain, and channel between them) is silicon (doped with P or B, depending on whether it’s a n- or p- channel). The gate is some form of SiO2 (i.e. glass). Metal or heavily doped polysilicon connects to the gate, the source, and the drain and is used to wire the transistors together.
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Do you know for sure if the gate in most FinFET processes is SiO2? I know that everyone had switched over to high-K / metal gate for planar transistors in the nodes prior to FinFET but it's never been clear to me if that change in materials carried over.
 
mr_roboto said:
Do you know for sure if the gate in most FinFET processes is SiO2? I know that everyone had switched over to high-K / metal gate for planar transistors in the nodes prior to FinFET but it's never been clear to me if that change in materials carried over.
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I assumed it was something like fluorine-doped SiO2 but I guess I don’t know for sure. Most other high-K dielectrics are pretty soft (which makes them not good for non-planar transistors), though I suppose they could be using something like HfOx.
 
Cmaier said:
We once did a design that was intended to be fab-able by two different foundries, but the foundries were pretty close in terms of their design rules, and we were able to come up with a least-common-denominator set of rules that allowed it to work. Can’t see how you could do that sort of thing with FINFETs, though, unless Intel has gone out of its way to provide a cell library that is 1:1 to TSMC’s.
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I still wonder if this might be the case of Intel gets to fab X, and TSMC continues to fab Y. For example, sending Intel the C1 and N1 follow-on chips.

Especially since the report doesn't say what Intel is fabbing, the article just assumes it might be the larger SoCs because of Kuo's comments from a year ago.

Cmaier said:
I wonder how much they automate stuff there.
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This is certainly a thought. Assuming they could get the two fabs within some margin of each other using automated conversions/etc, they could effectively "bin" them by fab as well.
 
mr_roboto said:
Do you know for sure if the gate in most FinFET processes is SiO2? I know that everyone had switched over to high-K / metal gate for planar transistors in the nodes prior to FinFET but it's never been clear to me if that change in materials carried over.
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reading some papers, looks like it might be a thin layer of SiO2, closest to the channel, surrounded by thicker HfO2.
 
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