May 7 “Let Loose” Event - new iPads

dada_dave said:
I was wondering if it might improve the Apple pencil experience, people pay a lot of money to add textured covers to their iPads to get a more paper-like writing surface.
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According to TechCrunch, some improvement but not paper-like.

The nano-texture glass brings an extra level of tactility to the table. The add-on does not give the Apple Pencil a paper-like experience, but it does add a touch of welcome friction to the otherwise entirely smooth experience.
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techcrunch.com

Apple iPad Pro M4 vs. iPad Air M2: Reviewing which is right for most | TechCrunch

Apple iPad Pro M4 and iPad M2 review comparison. Does OLED and a new chip justify the $500 premium for the new Pro?
techcrunch.com techcrunch.com
 
leman said:
There had to communication between the companies. Nothing else just makes sense to me. It is just way too convenient that GB6 adds SME support just few weeks before M4 is released, and that PrimateLabs manages to randomly guess the exact feature sets and test strings for these features.
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I can already see this being spun. “Applebench” they’ll cry.
 
Jimmyjames said:
I can already see this being spun. “Applebench” they’ll cry.
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I don’t think I buy it. Even at AMD we didn’t do that sort of thing, and we were selling processors (and Apple does not).
 
Cmaier said:
I don’t think I buy it. Even at AMD we didn’t do that sort of thing, and we were selling processors (and Apple does not).
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Hard to know. It does seem like a coincidence. Perhaps they read the tea leaves? I recall Hector Martin guessing something about Apple moving on from AMX recently. Intriguing nonetheless.
 
Andropov said:
It's immensely funny that this is happening at the same time Intel is being forced to drop AVX-512 because it's too big to support it on their smaller cores and having different instruction support for different types of cores in heterogeneous processors is simply too difficult to handle for the OS scheduler (or it hasn't been done).
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I think I get what you are trying to say here, but this is more a fundamental issue of a process being moved mid-execution between two cores with different capabilities, and not being aware of the change in capabilities. So end result is if you cached the availability of AVX512, get moved to the smaller core without it during a preemptive switch, and then tried to use the instructions you just asked about before the switch occurred, you just crash. And that process state is not something the OS can go fix.

There are ways to do it, but the more I think about it, the more of a mess it becomes. It's just easier to keep the cores instruction compatible than trying to get folks to fix their code to not only be responding to signals that the core type has changed, but also making any state that is generated from checking CPU feature bits per-thread, rather than per-process. Intel's not the only one that faced this problem. There were Android devices that had missing capabilities on the efficiency cores which would cause certain processes to crash.
 
Nycturne said:
I think I get what you are trying to say here, but this is more a fundamental issue of a process being moved mid-execution between two cores with different capabilities, and not being aware of the change in capabilities. So end result is if you cached the availability of AVX512, get moved to the smaller core without it during a preemptive switch, and then tried to use the instructions you just asked about before the switch occurred, you just crash. And that process state is not something the OS can go fix.

There are ways to do it, but the more I think about it, the more of a mess it becomes. It's just easier to keep the cores instruction compatible than trying to get folks to fix their code to not only be responding to signals that the core type has changed, but also making any state that is generated from checking CPU feature bits per-thread, rather than per-process. Intel's not the only one that faced this problem. There were Android devices that had missing capabilities on the efficiency cores which would cause certain processes to crash.
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well, the big boy way of handling this is to keep track of each thread’s requirements, and each core’s capabilities, and not schedule in such a way that a thread can be moved to a core that can’t handle the instructions in the thread. I mean, if I design some ALUs without a multipliers and some with a multiplier, and a multiply instructions comes along, my scheduler better not issue the multiply to an ALU that can’t handle the instruction. And the same should happen at the core level.
 
Nycturne said:
end result is if you cached the availability of AVX512, get moved to the smaller core without it during a preemptive switch, and then tried to use the instructions you just asked about before the switch occurred, you just crash
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Seriously? They have not figured out how to do unimplemented instruction exceptions? What, is this kindergarteners-with-crayons software design?
 
Nycturne said:
I think I get what you are trying to say here, but this is more a fundamental issue of a process being moved mid-execution between two cores with different capabilities, and not being aware of the change in capabilities. So end result is if you cached the availability of AVX512, get moved to the smaller core without it during a preemptive switch, and then tried to use the instructions you just asked about before the switch occurred, you just crash. And that process state is not something the OS can go fix.
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Yeah, that's what I meant. Even without caching the availability of AVX512, the scheduler could still move the thread between the instruction availability check and the instruction dispatch.

Cmaier said:
well, the big boy way of handling this is to keep track of each thread’s requirements, and each core’s capabilities, and not schedule in such a way that a thread can be moved to a core that can’t handle the instructions in the thread. I mean, if I design some ALUs without a multipliers and some with a multiplier, and a multiply instructions comes along, my scheduler better not issue the multiply to an ALU that can’t handle the instruction. And the same should happen at the core level.
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How would the OS know whether a thread is going to require AVX512 or not ahead of time? As @Nycturne above, I can think of ways to do it, but all or them are messy in some way...
 
leman said:
A lot of repetitive clicking :D That's why I only include a few dozen results. GB browser does allow you to download a json version of the report, but you need to have an account and I couldn't figure out how to download them using cURL (cookies don't seem to work). Since I only had 30 minutes to do all this, manually downloading the files was the quickest option.
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I'm sorry man I'm blind and I can't find where to download the JSON files 🤦‍♂️, I've got an account now, I'm sure it's obvious but I can't find it.
 
Geekerwan again?

iPad16,3 - Geekbench

Benchmark results for an iPad16,3 with an ARM processor.
browser.geekbench.com
1715773132560.png
 
Andropov said:
Yeah, that's what I meant. Even without caching the availability of AVX512, the scheduler could still move the thread between the instruction availability check and the instruction dispatch.


How would the OS know whether a thread is going to require AVX512 or not ahead of time? As @Nycturne above, I can think of ways to do it, but all or them are messy in some way...
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Well the binary is there and the instructions are encoded in the binary. Lots of ways to do it, and yes many are messy. But intel isn’t helping.
 
New ipad arrived. setting it up now. (it’s installing an out-of-the-box software update. My cellular plan allegedly transferred fine).

It is as thin and light as advertised. I don’t feel any flex or anything - feels solid. Pencil Pro looks and feels exactly the same as Pencil 2. Magnets are in different positions, so it doesn’t stick quite right to older iPad Pros.

The new keyboard case feels very nice, but I haven’t had a chance to type on it yet. It does still feel heavy, and overall weight of the combination feels like a macbook still.
 

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