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One more question @Cmaier, if I may. We've seen Intel follow Apple's lead with Alder Lake implementing big.LITTLE aka heterogeneous computing. The latest rumors claim that AMD is going the same route with Zen 5. What do you think the chances are of Apple taking a page from the x86 guys and implementing SMT? Does it make sense for their design, and if so, do you think we'd see it in both the performance and efficiency cores?
I don’t think it makes a lot of sense for Apple, given that Apple seems to have no trouble keeping every ALU busy at all times as it is. I’ve always felt that SMT was a crutch for designs where you can’t keep the ALUs busy because you have to many interruptions of the pipeline. x86 benefits from SMT because instruction decoding is so hard that you end up creating bubbles in the front end of the instruction stream. You fetch X bytes from the instruction cache and you never know how many instructions that corresponds to.
SMT on Arm, or at least on Apple’s processors so far, would just mean you are stopping one thread that was perfectly capable of continuing to run, in order to substitute in another. And paying the overhead for that swap. I think it would be a net negative.
That said, one could imagine doing SMT on the efficiency cores if the calculations show that you save power by reducing the complexity of the decode/dispatch hardware (thus creating bubbles) but can get back some performance without using up that power savings by doing SMT. That said, SMT also has other issues that need to be considered, including the likelihood that any SMT implementation will be susceptible to side channel attacks (and that mitigating against such attacks may require taking steps that mean the benefit is even less).