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I’ll skip the physics for now (unless anyone is interested) and jump to the advantages. The two biggest, from my perspective, were that you could shrink the physical size of circuits, and you reduced static power dissipation.I had to look up SOI, sounds interesting. What was nice about it and why don’t more fabs use it or still use it?
The former stems from the fact that you can push P-type and N-type transistors closer to each other - without SOI, particularly in the MOSFET era, you had to keep the P‘s and N’s fairly far apart and squeeze in electrical connections between the body of the transistor and ground. This took up a lot of space. By going to SOI, we were able to be very efficient in our cell designs, keeping each logic gate very small and not having to worry so much about how gates were arrayed next to each other.
As for power, the use of SOI greatly reduces leakage of current when the transistor is off.
It also solves problems like “latch up,” that required careful design to make sure that when you placed certain types of cells next to each other you didn’t accidentally create an unintentional latch.
As for whether anyone uses it now, I have no idea. I know it is heavily used in analog devices, but I don’t *think* the main cutting-edge logic fabs use it now. By switching from MOSFETs to FINFETs, and straining the silicon, you get a lot of the same benefits. The problem with SOI is probably cost - it’s hard to make a uniform, dislocation-free SOI wafer, especially a big one (like modern cuttting-edge fabs like to use).