Yes, the wall or someone testing the actual VRMs/power delivery is the best way to do this. That’s what Anandtech did for years with measuring A series power dominating rivals, you measure everything on down from the SoC to the package and DRAM to VRM/power stuff. These are all part of the product in a meaningful way, like how power costly DRAM accesses will vary based on L2 and SLC cache amounts, stuff like that.Could you elaborate? I'd be interested to know more. It's hard to empirically check the numbers coming from powermetrics as there's no other way to measure power (other than wall power) of a Mac
And well (see power section) powermetrics is modeled internally and it ain’t great. Andrei wouldn’t use it anyways because it misses out on DRAM as he realized but he rightly points out it doesn’t even do the CPU well.
The wall or ideally PMIC/VRMs is how the power is actually measured in all the tests everyone points to for years from Geekerwan and Andrei or Anand.I would be interested in any evidence you have for this? How exactly do you know power metrics is badly modelled and inaccurate? Why would the wall minus idle on a device with a battery be better.
I’m also a little surprised to hear that the M2 is using more power than previously reported, and that the M4’s power usage is cause for concern.
I’m honestly surprised people took it seriously, it’s nearly irrelevant. We basically have (some) Apple fans doing their own version of AMD/Intel guys reading HwInfo but it’s even worse because this is a game Apple and mobile vendors do better on.
I also want to point out that power metrics doesn’t even claim to measure DRAM anymore since a major MacOS update IME, which is funny. Even if it were accurate, it would be near worthless.
AMD and Intel’s modeling are better without a doubt but still not to be trusted at all and their fans still play games on this note.
Again, this is so funny because Apple fans (or just anyone opposed to AMD/Intel sloppiness like myself) should not want to play the game of excluding DRAM and power delivery or package losses!
So yes, it’s better because it reflects dependent variables to the chip itself (DRAM access rates) or just directly linked like again, DRAM and the power delivery setup.
It’s honestly profoundly annoying.