having done something like this (two different processes, albeit our own fabs), what ends up happening, probably, is you create your own “least common denominator” design rules that work with both fabs. But you inevitable give something up in doing this. For example, fab A might say minimum polygon area is 1nm^2 and minimum M0 spacing is 0,5nm, and fab B might say minimum polygon area is 1.2nm^2 and minimum M0 spacing is 0.3nm. So you end up with 1.2nm^2 and 0.5nm. Worst of both worlds.
And that’s assuming both processes give you equivalent number of metal layers and that the layer thicknesses are the same, dielectrics are the same, etc. If the layer thicknesses and dielectrics vary, then you have additional problems. You end up over engineering to make cycle time and satisfy hold times on both processes, and the design process takes a lot longer.