Just wanted to clarify that my estimate of >25 ns latency was a lower bound for the RAM timing only, so signaling and SoC logic aren't accounted for. I recall that when the Vision Pro was announced, there was vague talk of some kind of packaging tech (sounded like some sort of die to die bonding) that halved the latency between the R1 and RAM. So, to me that means that signaling and such take at least as much time as the RAM timing, meaning that the total latency lower bound for LPDDR5 and A17 Pro would be something like > 50 ns.What matters is the latency as seen by the CPU core. On average it will be nothing close to the RAM timing, because of caches. After all, that‘s the point of caches. So if memory gets 20% faster but your cache hit rate goes down by 40%, you aren’t helping yourself. So I tend to look at the memory subsystem holistically, taking into account page faults, cache misses, the different levels and sizes of cache (each with their own latencies and bandwidth), etc.