TSMC: 2nm using nanosheet transistors

[Cmaier]

TSMC announced this week the 2nm node will use nanosheets.

My highly detailed and accurate schematics illustrating the difference between nanosheet transistors, coming to the 2nm TSMC node, and FINFETs and MOSFETs, is below. The fact that the gate completely surrounds the channel should essentially eliminate leakage current, meaning that when transistors are not switching, they shouldn’t be burning any power. They should also switch faster, as the channel can be established (or eliminated) much more quickly since the electromagnetic field is coming from every direction.

Ideally each “sheet” would have a circular cross-section, but we don’t know how close to ideal TSMC’s process will achieve.

 

[Cmaier]

Looks like Samsung claims it will use nanosheet for 3nm. Intel appears to be planning to use nanosheet for its 2nm process.

It looks like Intel’s will be a forksheet - this is pretty similar to what i drew, but it only surrounds the fins on three sides because you put a huge dielectric (i.e. electrical insulator) on the other side, and use it to. Allow an other transistor of opposite polarity right next to it. CMOS circuits always have NFETs and PFETs (That’s what the “C” in CMOS means - “complementary”), and the closer you can put them together, the faster you can make the overall circuit. You give up a tiny bit because you aren’t applying an electric field from all sides, but the vertical side is small, so the loss is (hopefully) negligible.

The following image, obviously taken using the scanning tunneling electron microscope in my living room, indicates the difference. We don’t know what TSMC is going to do re: fork or not.

 

[Cmaier]

I should also add that you don’t *always* want to snuggle a PFET and NFET like that. An inverter (logical ”not”) has 1 PFET and 1 NFET that should abut. Other logic circuits have other requirements. A logical NAND gate would have 1 NFET that you want right up against TWO PFETs, and a second NAND gate that you wouldn’t want next to the PFETs, but would want next to the NFET. So if you are designing circuits, you need the ability to either put the dielectric where you want it, or you would have three different transistor objects: NFET, PFET, and pair. (And possibly other variations, like NFET pairs, PFET pairs, etc.). The methodology most like the days when I designed circuits would be that we would draw the fingers where we want, draw the gate where we want, and draw the dielectric pillar where we want, subject to rules provided by the fab. I doubt 2nm circuit designers will have that degree of freedom, given the manufacturing challenge involved in making sure these things work.

 

[Andropov]

My highly detailed and accurate schematics illustrating the difference between nanosheet transistors, coming to the 2nm TSMC node, and FINFETs and MOSFETs, is below. The fact that the gate completely surrounds the channel should essentially eliminate leakage current, meaning that when transistors are not switching, they shouldn’t be burning any power.

Will that translate into a significant reduction of static power once nanosheet-based SoCs arrive?

The following image, obviously taken using the scanning tunneling electron microscope in my living room, indicates the difference.

I actually got to control a tunneling electron microscope on the last year of my BSc. Very cool machines. Not as big as I had imagined, either. You could probably fit one in your living room for real, provided high enough ceilings
I was also surprised with how low-tech some parts of the process were. I remember that the day-to-day sharpening the tip of the probe was done by crashing it into the substrate and then slowly lifting it.

 

[Cmaier]

Will that translate into a significant reduction of static power once nanosheet-based SoCs arrive?


I actually got to control a tunneling electron microscope on the last year of my BSc. Very cool machines. Not as big as I had imagined, either. You could probably fit one in your living room for real, provided high enough ceilings
I was also surprised with how low-tech some parts of the process were. I remember that the day-to-day sharpening the tip of the probe was done by crashing it into the substrate and then slowly lifting it.

Yes, static power should reduce a lot. There’s still going to be some leakage if the gate widths are small - due to quantum effects all you can do is reduce the probability of electrons jumping over the channel, you can’t absolutely prevent any from doing so. And since the cross section will almost certainly be rectangular, there may be an opportunity for a little leakage far from the corners.

The reason I hedge is that there are competing factors. If you used fins on a 45nm part, you’d have no leakage at all. The reason they went to fins was to compensate for the quantum effects they introduced by shrinking the gate. So now they wrap the gate all the way around - does that merely keep up, or is it better than that? My semiconductor physics Intuition is that it is better than that - for now.

I think they will have to adjust the shape of the fins next. And they are going to run into a thermal problem soon. To get faster they will probably have to change the material in the channels. First they will badgap engineer it some more by introducing more strain. Then they may have to figure out a way to make use of iii-v semiconductors at least in the channels.

They may also have to get more creative about thinning the die so they can cool better out the back side, and maybe supply power through the backside too. Fun things.

 

[throAU]

The fact that the gate completely surrounds the channel should essentially eliminate leakage current, meaning that when transistors are not switching, they shouldn’t be burning any power. They should also switch faster, as the channel can be established (or eliminated) much more quickly since the electromagnetic field is coming from every direction.

So in end user talk.... potentially higher clocks, lower power draw and less heat... to a much more significant degree than a regular die shrink?

 

[Cmaier]

So in end user talk.... potentially higher clocks, lower power draw and less heat... to a much more significant degree than a regular die shrink?

Not clear to me. If you were to take, say, the 5nm process and redesign the transistors like this, you’d see a very nice increase in performance/watt (because the transistors will have a higher switching frequency at a given voltage, and the leakage current will decrease quite a bit).

The question is whether the shrink to 2nm causes such a spike in leakage that you need to do nano sheet just to keep up, or whether it offers an advantage beyond just breaking even.

My gut is that it should do better than you otherwise would get when going from 5nm to 2nm, if for no other reason than you can move the pfets much closer to the nfets (assuming they do forksheets). It also seems to me that the use of multiple vertically-separated strips is more than a break-even factor, as it increases the area over which current can flow (current flows on the outside of a conductor, so the more surface area, generally the better). One could imagine not stacking strips, and instead just wrapping the existing fin so that the bottom is touching the gate - that may be enough to cancel out the additional quantum effects caused by the shrink to 2nm, depending on the aspect ration of the fins; but it seems likely that TSMC will have a stack of strips, each surrounded on at least three sides by gate, including the high aspect ratio sides, which seems like more than would be required to cancel out the bad effects of the shrink.

There are a lot of things I don’t know yet, though. I hope TSMC publishes at least some information on the actual structure, the dielectric thicknesses, the doping of the channel, etc. With a little more information I can make a much more educated guess.

 

[Entropy]

Not clear to me. If you were to take, say, the 5nm process and redesign the transistors like this, you’d see a very nice increase in performance/watt (because the transistors will have a higher switching frequency at a given voltage, and the leakage current will decrease quite a bit).

The question is whether the shrink to 2nm causes such a spike in leakage that you need to do nano sheet just to keep up, or whether it offers an advantage beyond just breaking even.

My gut is that it should do better than you otherwise would get when going from 5nm to 2nm, if for no other reason than you can move the pfets much closer to the nfets (assuming they do forksheets). It also seems to me that the use of multiple vertically-separated strips is more than a break-even factor, as it increases the area over which current can flow (current flows on the outside of a conductor, so the more surface area, generally the better). One could imagine not stacking strips, and instead just wrapping the existing fin so that the bottom is touching the gate - that may be enough to cancel out the additional quantum effects caused by the shrink to 2nm, depending on the aspect ration of the fins; but it seems likely that TSMC will have a stack of strips, each surrounded on at least three sides by gate, including the high aspect ratio sides, which seems like more than would be required to cancel out the bad effects of the shrink.

There are a lot of things I don’t know yet, though. I hope TSMC publishes at least some information on the actual structure, the dielectric thicknesses, the doping of the channel, etc. With a little more information I can make a much more educated guess.

I have been observing the slowing of SRAM scaling with some concern. IMEC had some material that proposed different GAA based SRAM cells, where the smallest was quite dense, but also seemed...challenging...in terms of manufacture. TSMC was quoted as giving a 1.1 times scaling from 3nm to 2nm, which is basically nothing (although that single figure is awfully vague). So it seems that they are proposing their first GAA generation as an improvement of power/performance and not area. Manufacturability is key, so it makes sense.
Have to say that from my dilettante viewpoint the lithographic crystal ball is awfully murky going forward. There are a number of proposed techniques, but which will pan out, and what they will yield is basically totally opaque.

 

[Cmaier]

I have been observing the slowing of SRAM scaling with some concern. IMEC had some material that proposed different GAA based SRAM cells, where the smallest was quite dense, but also seemed...challenging...in terms of manufacture. TSMC was quoted as giving a 1.1 times scaling from 3nm to 2nm, which is basically nothing (although that single figure is awfully vague). So it seems that they are proposing their first GAA generation as an improvement of power/performance and not area. Manufacturability is key, so it makes sense.
Have to say that from my dilettante viewpoint the lithographic crystal ball is awfully murky going forward. There are a number of proposed techniques, but which will pan out, and what they will yield is basically totally opaque.

Even if you didn’t shrink the node - just going from 3nm FINFET to 3nm GAA should should result in much more dense SRAM. The PFETs typically are close to 1:1 width to length, but the NFETs (in the stack) are closer to 2:1 width to length, so instead of going laterally to get that you can get that with the vertical stack (one of the advantages of those stacked horizontal nanosheets is you increase W:L).

And an SRAM is two pairs of PFET/NFETs, plus two NFET pass transistors. Those two pairs should work out very nicely with fork sheets. So depending on what you were coming from, i could imagine a 33% reduction in SRAM cell size without shrinking the gate lengths. I figure a FINFET SRAM stack has 1x space for the PFET and 2x space for the NFET (roughly), and you can change that to 1x for each with the GAA (roughly). So 3->2. If you are not currently using silicon-on-insulator, the savings from going to forksheet would be even more.

Amusingly, after writing this, I searched for technical papers on GAA SRAM layouts. The first one I found compared a layout at 10nm for GAA and FINFET, and they saved 16% area for a *half* SRAM cell (so 32% for a full one). That paper didn’t use forksheets.

 

[theorist9]

TSMC announced this week the 2nm node will use nanosheets.

My highly detailed and accurate schematics illustrating the difference between nanosheet transistors, coming to the 2nm TSMC node, and FINFETs and MOSFETs, is below. The fact that the gate completely surrounds the channel should essentially eliminate leakage current, meaning that when transistors are not switching, they shouldn’t be burning any power. They should also switch faster, as the channel can be established (or eliminated) much more quickly since the electromagnetic field is coming from every direction.

Ideally each “sheet” would have a circular cross-section, but we don’t know how close to ideal TSMC’s process will achieve.

View attachment 15054

Would it be possible to add some dimensions to the FinFet and nanosheet diagrams, assuming TSMC's 3 nm process for the FinFet, and 2 nm for the nanosheets? It would be interesting to see, even approximately, how these 3 nm and 2 nm marketing terms compare to the actual device sizes.

Based on https://semiwiki.com/semiconductor-...derations-for-gate-all-around-gaa-technology/ , it looks like the gray drain and source on your FinFit diagram are the fin, and the the depth of that gray rectangular solid would be the fin thickness, which they specified as 6 nm. But is that for the N5 process?

For the nanosheets they have this diagram (and I assume it's for the 2 nm process), but I'm not quite sure how to translate the dimensions they list to the dimensions on the diagram. For instance, they say "FW=H_NS = 6 nm", where H_NS sounds like the height of the nanosheet, but I'm not sure how they're defining that height—is it the thickness, or the center-to-center spacing? I measured the width and the thickness in the photo, and the thickness is 1/10 the width, so 55 nm/10 implies 6 nm refers to the nanosheet thickness, in which case the thickness of the nanosheets in the 2 nm process is the same ( 6 nm) as that of the FinFet fins in whatever process they're depicting for those.

 

[Cmaier]

Would it be possible to add some dimensions to the FinFet and nanosheet diagrams, assuming TSMC's 3 nm process for the FinFet, and 2 nm for the nanosheets? It would be interesting to see, even approximately, how these 3 nm and 2 nm marketing terms compare to the actual device sizes.

Based on https://semiwiki.com/semiconductor-...derations-for-gate-all-around-gaa-technology/ , it looks like the gray drain and source on your FinFit diagram are the fin, and the the depth of that gray rectangular solid would be the fin thickness, which they specified as 6 nm. But is that for the N5 process?

For the nanosheets they have this diagram (and I assume it's for the 2 nm process), but I'm not quite sure how to translate the dimensions they list to the dimensions on the diagram. For instance, they say "FW=H_NS = 6 nm", where H_NS sounds like the height of the nanosheet, but I'm not sure how they're defining that height—is it the thickness, or the center-to-center spacing? I measured the width and the thickness in the photo, and the thickness is 1/10 the width, so 55 nm/10 implies 6 nm refers to the nanosheet thickness, in which case the thickness of the nanosheets in the 2 nm process is the same ( 6 nm) as that of the FinFet fins in whatever process they're depicting for those.

View attachment 15290

Yeah, the source/drain are the parts of the fin outside the channel. When we talk about width/length of a transistor, we are talking about the channel. So:

When you talk about a 7nm process, that used to mean that L could be as small as 7nm. Nowadays it’s a lot more fuzzy.

”Hns” does apparently mean the “height of the device,” which is a little vague to me. I do see some papers that suggest that, in 3nm, most of the processes have settled on a stack of three fins and an Hns of 55nm. It seems that there has been some confusion about what to call these dimensions, but most likely:

FP = fin pitch (center to center distance)
FH = fin height (i.e. the thickness of each of those 3 fins I drew)
FW = fin width (or what I was calling W)

As for the actual values, I don’t know if that table is accurate.

 

[Cmaier]

FWIW, looks to me like in TSMC’s 5nm node, the minimum gate length is around 16nm.

It’s kind of hard to compare FINFET nodes to MOSFET nodes (and to compare nano sheet nodes to both of them) because what us CPU designers care about is the ratio of W to L (and the absolute value of L, and the ratio of the height (or the collective height of the fins) to the spacing between fins horizontally. Since there are multiple channels (one for each fin), the “effective” channel width/length ratio is a mathematical function that depends on the geometry of the fins. So you can be increasing W/L without actually shrinking L or making W bigger. The higher the W/L, the more current you can drive through the drain (and the faster you can charge and discharge wires/downstream gates). Current is a linear function of W/L. So fitting more W/L in the same area is, in many ways, equivalent to actually physically shrinking L.

 

[Yoused]

These graphics always seem to confuse me. FinFET and GAA where ever I see them, make it look like the Vss and Vdd leads are continuous. The MOSFET images I have seen in the past are clearer about that, depicting the gate as a sort of substrate-like thing with the source and drain leads kind of like lying on top, with a gap.

The word "gate" is kind of confusing in and of itself: I think of a gate as a sort of gumdrop with some inputs at the wide end and an output at the apex, which is a competely different animal (an abstraction) from these FET things.

 

[Cmaier]

These graphics always seem to confuse me. FinFET and GAA where ever I see them, make it look like the Vss and Vdd leads are continuous. The MOSFET images I have seen in the past are clearer about that, depicting the gate as a sort of substrate-like thing with the source and drain leads kind of like lying on top, with a gap.

The word "gate" is kind of confusing in and of itself: I think of a gate as a sort of gumdrop with some inputs at the wide end and an output at the apex, which is a competely different animal (an abstraction) from these FET things.

I like to think of it as a garden hose. The source is the spigot, and the drain is the opposite end. The gate is your foot. If you press down with your foot just from the top (like in a MOSFET), you can’t completely close off the hose, and some liquid leaks through. If you squeeze from all sides, that’s like a GAA.

 

[Yoused]

This is kinda the way I understood MOSFET

 

[Cmaier]

This is kinda the way I understood MOSFET

View attachment 15305​

Well, it sort of depends on whether we are talking about depletion mode MOSFETs or enhancement mode MOSFETs, but either way I’m not sure the above is the best analogy.

There are holes and electrons on both sides of the gate, and the electrons want to flow one way (say left to right) and the holes the other way, depending on the voltage difference between the source and drain. I think of voltage sort of like elevation; electrons like to flow down hill, and holes like to flow up hill.

The channel (the green region, which would be the region under the gate metal), is like a valve that can be opened or closed, either allowing the current to flow through or not. I think the last sentence is referring to what we call recombination, but I’m not quite sure.

In any event, the particulars of the gate are that you have a semiconductor region on the bottom. Above it is an insulator (SiO2), and above that is conductor (poly silicon and/or metal). This forms a capacitor, with the green area as the bottom plate, and the conductor as the top plate. If you put, say, a positive charge on the top plate, it induces a negative charge on the bottom plate, because it repels holes and attracts electrons that happen to be hanging out in the channel region. This forms a thin layer at the top of the green area that has an elevated amount of charge carriers of one type or the other.

So If we’ve induced negative charge, then it’s safe for electrons to cross the channel. Or if we induce holes, it’s safe for holes to cross. This allows current to flow in a direction determined by the voltage difference between the source and drain.

In modern transistors it gets more complicated, because you add in some germanium. This induces strain in the crystal lattice, which causes a kink in the conduction and valence bands - that’s a complicated way of saying that it causes a situation where you’ve greatly increased the ability of one type of carrier to move (it’s “mobility”) while decreasing the mobility of the other kind of carrier. This amplifies the current that you can get through the channel. And, even in regular silicon, the mobility of electrons is much higher than holes. (We often approximate the ratio as 2:1, but that’s not super-precise. In other materials, like III-V semiconductors, it can be much higher).

 

[theorist9]

They may also have to get more creative about thinning the die so they can cool better out the back side, and maybe supply power through the backside too. Fun things.

More on backside power delivery from Anton Shilov at Anandtech, published today:

"Unlike some of their rivals...the first iteration of N2 will only be implementing gate-all-around transistors, with backside power delivery to come with a later version of the node....[A] backside power rail [enables] improved power delivery to transistors, which increases performance and lowers power consumption..... but will ultimately add additional process steps, which the company is seemingly looking to avoid on their first try with GAAFETs....

...The lack of backside power delivery in the original version of the N2 fabrication technology perhaps explains rather moderate performance improvement of N2 when compared to N3E node. While for high-performance computing (CPUs, accelerators, etc.) a 10% to 15% performance improvement at the same power and complexity does not seem to be impressive, a 25% to 30% power drop at the same speed and complexity seems to be very good for mobile applications....

...This will end up being a notable difference from how rival Intel is planning to handle their own GAAFET/backside power transition with the Intel 20A process. Intel intends to introduce its GAA RibbonFET transistors and PowerVia interconnects together in mid-2024 – going so far as to create an internal pseudo node just to focus on RibbonFET development "

TSMC: N2 To Start With Just GAAFETs, Add Backside Power Delivery Later

www.anandtech.com

 

[Cmaier]

More on backside power delivery:

"Unlike some of their rivals...the first iteration of N2 will only be implementing gate-all-around transistors, with backside power delivery to come with a later version of the node....a backside power rail [enables] improved power delivery to transistors, which increases performance and lowers power consumption..... but will ultimately add additional process steps, which the company is seemingly looking to avoid on their first try with GAAFETs....

...The lack of backside power delivery in the original version of the N2 fabrication technology perhaps explains rather moderate performance improvement of N2 when compared to N3E node. While for high-performance computing (CPUs, accelerators, etc.) a 10% to 15% performance improvement at the same power and complexity does not seem to be impressive, a 25% to 30% power drop at the same speed and complexity seems to be very good for mobile applications....

...This will end up being a notable difference from how rival Intel is planning to handle their own GAAFET/backside power transition with the Intel 20A process. Intel intends to introduce its GAA RibbonFET transistors and PowerVia interconnects together in mid-2024 – going so far as to create an internal pseudo node just to focus on RibbonFET development "

TSMC: N2 To Start With Just GAAFETs, Add Backside Power Delivery Later

www.anandtech.com

I’m at a loss as to why backside power would have a really huge effect. There are two effects you see mentioned. One is what we used to call IR drop. There are lots of ways to attack that, though - on Opteron we had an entire metal layer dedicated to each of Vss and Vdd, and these were also useful to eliminate signal cross-coupling. The other effect you see mentioned is cell area. But I would bet you really can’t squeeze the cells as much as the tech press likes to speculate, because of signal cross-coupling and IR drop. You want to shield a lot of signal lines with power or ground, and you want to spread the current on the front side as well as the backside.

I don’t know how the industry intends to handle it, but if they have to thin the silicon to allow backside power, then that, by itself, could have interesting thermal implications, as it allows improved cooling out the backside of the die.

 

[theorist9]

I don’t know how the industry intends to handle it, but if they have to thin the silicon to allow backside power, then that, by itself, could have interesting thermal implications, as it allows improved cooling out the backside of the die.

Given how important cooling is, if thinning is possible wouldn't they do that anyways?

And are nanosheets inherently thinner than current Si wafers and, if so, would that give them inherently better cooling (even without additional thinning work)?

 

[Cmaier]

Given how important cooling is, if thinning is possible wouldn't they do that anyways?

And are nanosheets inherently thinner than current Si wafers and, if so, would that give them inherently better cooling (even without additional thinning work)?

It is not cheap to do the thinning and there are physical trade offs (dies can crack, etc.). Sometimes you do something like silicon-on-insulator and don’t want to thin because you are relying on the insulator for substrate isolation. What you are doing is removing material from the substrate side, which isn’t cheap. They do it a lot in LED wafers, but those are much simpler devices so less chance of breaking something.

Anyway, nano sheets aren’t going to be any thinner than current wafers. Most of the thickness of the chip is the substrate. The active chip area is a very very thin layer on top.

There should be some improved backside cooling even without thinning, since the metal power supply going through the vias to the back will conduct heat.