TSMC: 2nm using nanosheet transistors

Entropy said:
I have been observing the slowing of SRAM scaling with some concern. IMEC had some material that proposed different GAA based SRAM cells, where the smallest was quite dense, but also seemed...challenging...in terms of manufacture. TSMC was quoted as giving a 1.1 times scaling from 3nm to 2nm, which is basically nothing (although that single figure is awfully vague). So it seems that they are proposing their first GAA generation as an improvement of power/performance and not area. Manufacturability is key, so it makes sense.
Have to say that from my dilettante viewpoint the lithographic crystal ball is awfully murky going forward. There are a number of proposed techniques, but which will pan out, and what they will yield is basically totally opaque.
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Returning to this, it appears poor SRAM scaling will also impact N3. According David Schor of WikiChip ( https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-witness-the-death-of-sram/ ), SRAM scaling from N5 to N3B (the first gen TSMC 3 nm process) is only 1.05; and from N5 to N3E (2nd gen 3 nm), it's 1.0 (N3E is somewhat larger than N3B). If a typical chip is 60% logic and 40% SRAM (as this article's hypothetical suggests), that would seem to be a big deal.

Here's a summary of the WikiChip article from Anton Shilov: https://www.tomshardware.com/news/no-sram-scaling-implies-on-more-expensive-cpus-and-gpus
 
I have a question for @Cmaier: to what extent is there a harmonic correlation between wire-lead length and frequency? Is there an optimal pitch at which a certain clock speed works best, kind of like the way a laser cavity works best at a length that matches up with the light wavelength (but not quite exactly like that)?
 
Yoused said:
I have a question for @Cmaier: to what extent is there a harmonic correlation between wire-lead length and frequency? Is there an optimal pitch at which a certain clock speed works best, kind of like the way a laser cavity works best at a length that matches up with the light wavelength (but not quite exactly like that)?
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No not really. Individual wires act mostly like capacitors, but also like transmission lines.l to a secondary degree (in the on-chip regime, at least). We worry about creating giant loops, too, but all of that is for discrete physical effects. There’s no sort of feedback effect where you get something like resonance. Longer wires always make things worse (exponentially or linearly, depending on whether capacitance or transmission line dominates).

Pitch is a different issue from length. Bigger pitch is better (less sidewall capacitance) but will tend to push things farther apart, meaning longer wire lengths. So, if you have a fixed number of metal layers and you are only turning the “die area” and “metal pitch” knobs, there you WILL find some interesting interactions if you are measuring the resulting frequency. Of course it’s sort of meaningless because you would adjust other things to compensate in real life, and there are upper and lower limits on pitch (too little and you can’t get the lithography to work. Too much and your layers start to cave in between the wires, destroying your yield).
 
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