CFET news

[Cmaier]

Intel and TSMC to Report on Next-Gen CFET Transistor Progress

Intel and TSMC to present papers covering complementary field effect transistors.

www.tomshardware.com

I’m still looking for someone to show information about gates other than inverters, but it looks like progress is being made. If you are going to stack nfets on pfets, though, I am very curious how the nfets perform vs nfets that are not over pfets. For a lot of logic gates, you won’t always be able to stack.

 

[Yoused]

For the ones that you can stack, I assume this would draw a little less juice the way CMOS is more energy efficient than NMOS, but it seems like the apparently larger feature size would result in a little more draw. Would it balance out, in the end?

 

[Cmaier]

For the ones that you can stack, I assume this would draw a little less juice the way CMOS is more energy efficient than NMOS, but it seems like the apparently larger feature size would result in a little more draw. Would it balance out, in the end?

well, all the gates i was thinking of are cmos, so there is always stacking of some sort in the logical sense; i just don’t know that it always makes sense to physically stack.

In an inverter you have two transistors - an NFET and a PFET. Their gates are attached to each other, as are their sources. Their drains are attached to opposite power rails (power/ground). Pretty awesome way to use a CFET instead. Run the gate and source wires straight through, and you’re golden.

But then you get into more complicate situations. A simple 2-input NAND gate is a logical stack, but the stack consists of two series-connected NFETS on the one hand, and two parallel-connected PFETS on the other. Each NFET has a corresponding PFET that shares a gate connection, and I guess you’d turn that into a CFET. But their source/drain connections vary depending on which CFET you’re talking about. So that increases the metallization complexity.

As you get into more and more complicated CMOS gates, you get into situations where there aren’t necessarily easy PFET/NFET buddies to pair up, or where there are pairs, but getting the metal to work out might require more trouble than it’s worth - forcing you to spread things apart.

The next time I have some free time I’m going to break out some graph paper and think about how some of these gates could be optimixed. My guess is it would be a net win (assuming the CFET performance doesn’t degrade from NFET/PFET performance just by virtue of each of these NFET portions having a wavy, not-quite-planar base underneath them.)

And what’s going to torment engineering students and newborn CPU designers is when you draw schematic diagrams for CMOS you put the PFET stacks on top of the NFET stacks, but physically it looks like it will be NFETs on top of PFETs. I wonder if people will start doing circuit schematics with ground on top and power on the bottom