M4 Rumors (requests for).

[theorist9]

Gurman continues to predict that the M4 won't appear in the Studio and MP until H2 2025:

"M4-based Mac Pro and Mac Studio still on track for latter half of next year. There’s been speculation online about when to expect the M4 Mac line, which I first discussed months ago. After checking around, I don’t see a change in schedule. The M4 iMacs, MacBook Pros (low- and high-end versions) and Mac minis (low- and high-end models as well) are due between the end of 2024 and early 2025. New MacBook Airs are coming in the spring of 2025, and the Mac Pro and Mac Studio models will arrive around the second half of next year. This will mark the first time Apple is bringing a new chip family to every Mac it makes. The move follows the addition of the M4 to the iPad Pro in May."

From Bloomberg, June 23, 2024.

Bloomberg - Are you a robot?

 

[Cmaier]

Gurman continues to predict that the M4 won't appear in the Studio and MP until H2 2025:

"M4-based Mac Pro and Mac Studio still on track for latter half of next year. There’s been speculation online about when to expect the M4 Mac line, which I first discussed months ago. After checking around, I don’t see a change in schedule. The M4 iMacs, MacBook Pros (low- and high-end versions) and Mac minis (low- and high-end models as well) are due between the end of 2024 and early 2025. New MacBook Airs are coming in the spring of 2025, and the Mac Pro and Mac Studio models will arrive around the second half of next year. This will mark the first time Apple is bringing a new chip family to every Mac it makes. The move follows the addition of the M4 to the iPad Pro in May."

From Bloomberg, June 23, 2024.

Bloomberg - Are you a robot?

Apple’s release schedule has gotten very strange. But I imagine H2 2025 means July and not December.

 

[theorist9]

Apple’s release schedule has gotten very strange. But I imagine H2 2025 means July and not December.

I'd expect that as well (or even at WWDC in June), unless the Studio and MP are instead on M5.

 

[Yoused]

unless the Studio and MP are instead on M5

Given Apple's big new "AI" push,

Spoiler: M5 Mac Pro

(hopefully Captain Kirk will not be able to talk it to death as he has done so often)

 

[theorist9]

Given Apple's big new "AI" push,

Spoiler: M5 Mac Pro

(hopefully Captain Kirk will not be able to talk it to death as he has done so often)

If you want to see what Apple's really been working on, go to O'Reilly Auto Parts and search for 121G.

 

[The Hardcard]

One possible reason for H2 2025. It would line up with using SoIC for the next Ultras.

SoIC plans.

SoIC tech.

 

[jbailey]

If you want to see what Apple's really been working on, go to O'Reilly Auto Parts and search for 121G.

Nah, Apple abandoned their car project.

 

[theorist9]

One possible reason for H2 2025. It would line up with using SoIC for the next Ultras.

SoIC plans.

SoIC tech.

So it's essentially 3D SoC, where by 2025 they're saying they can overlay an N3 chip on top of an N4 chip. That may require an overly high development cost for what has thus far been a low-volume chip. The current Ultra uses Max chips, so no new chip arch is needed. But this design couldn't combine two Max's, since it's N3+N4.

 

[Cmaier]

So it's essentially 3D SoC, where by 2025 they're saying they can overlay an N3 chip on top of an N4 chip. That may require an overly high development cost for what has thus far been a low-volume chip. The current Ultra uses Max chips, so no new chip arch is needed. But this design couldn't combine two Max's, since it's N3+N4.

Rumor is this is going too happen with M5

 

[theorist9]

Rumor is this is going too happen with M5

Is the rumor that they'll be using it only where it's needed to bypass the reticle limit (i.e., in Ultra-sized chips), or that they'll be using it across their line to improve performance, by reducing connection length between features where that distance matters; I don't know where that would help, but maybe putting CPU cache just above or below the CPU cores instead of to their sides, to reduce latency?

Edit: Just found this, https://www.macrumors.com/2024/07/04/apple-m5-chips-advanced-packaging-tsmc/ , which says:

"Currently, Apple's AI cloud servers are believed to be running on multiple connected M2 Ultra chips, which were originally designed solely for desktop Macs. Whenever the M5 is adopted, its advanced dual-use design is believed to be a sign of Apple future-proofing its plan to vertically integrate its supply chain for AI functionality across computers, cloud servers, and software."

If so, that would greatly improve the economies of scale for the Ultra, and justify moving to a design with higher development costs, such as SoIC.

 

[The Hardcard]

Is the rumor that they'll be using it only where it's needed to bypass the reticle limit (i.e., in Ultra-sized chips), or that they'll be using it across their line to improve performance, by reducing connection length between features where that distance matters; I don't know where that would help, but maybe putting CPU cache just above or below the CPU cores instead of to their sides, to reduce latency?

Edit: Just found this, https://www.macrumors.com/2024/07/04/apple-m5-chips-advanced-packaging-tsmc/ , which says:

"Currently, Apple's AI cloud servers are believed to be running on multiple connected M2 Ultra chips, which were originally designed solely for desktop Macs. Whenever the M5 is adopted, its advanced dual-use design is believed to be a sign of Apple future-proofing its plan to vertically integrate its supply chain for AI functionality across computers, cloud servers, and software."

If so, that would greatly improve the economies of scale for the Ultra, and justify moving to a design with higher development costs, such as SoIC.

Among the claims made by TSMC is that SoIC reduces PCB costs, so the extra development costs could be made back. More than made back with datacenter deployment.

A year is a long wait for something I want to see now. I hope it can at least be announced and described by next WWDC.

 

[Cmaier]

Among the claims made by TSMC is that SoIC reduces PCB costs, so the extra development costs could be made back. More than made back with datacenter deployment.

A year is a long wait for something I want to see now. I hope it can at least be announced and described by next WWDC.

I’m guessing they won’t use SoIC to stack CPU-die, and will instead put the RAM on top of the CPU (like they do for a bunch of their chips now). The cooling would be problematic, and there isn’t much advantage to doing it that way. Not unless they plan to re-do things so that, for example, one die is all CPU cores+cache, and another die is all GPU cores and neural.

 

[leman]

I’m guessing they won’t use SoIC to stack CPU-die, and will instead put the RAM on top of the CPU (like they do for a bunch of their chips now). The cooling would be problematic, and there isn’t much advantage to doing it that way. Not unless they plan to re-do things so that, for example, one die is all CPU cores+cache, and another die is all GPU cores and neural.

I think the likely split is a logic die (N3) + a "controller" die that contains cache, memory controllers, I/O, etc. (N4/N5). That would allow them to address two challenges: compute density (especially compared to dedicated products like GPUs) and the lack of scaling for SRAM on newer nodes. The cost of a 3D package would be high but considerably lower than that of a similar product on a monolithic newest-process die. It has always been my opinion that the ability to absorb higher manufacturing costs is a decisive advantage for Apple.

They describe this type of strategy in several patents, most notably in https://patentscope.wipo.int/search/en/detail.jsf?docId=US411171342&_cid=P20-LY8BVA-11220-1

Other possible uses for 3D chip stacking include:

- building larger systems (aka Ultra) from smaller SoCs — I am skeptical about this as the thermals will be bad, and I just don't see the advantage compared to the current 2D arrangement
- using the economy of scale to split CPU and GPU dies and combine them flexibly to build various SoCs. This is a potentially compelling strategy. I am just not sure it is economically viable — you might save some money making basic building blocks, but you'll have to invest more for variable packaging. Also, across the various die interconnect patents Apple has published, they always talk about asymmetrical high-performance die and low-performance die, never about combining two high-performance dies.

 

[Cmaier]

SRAM might not scale well on N3, but it’s still more dense, faster, and power efficient than on N4. I think they keep cache with the critical logic.

 

[Yoused]

The cooling would be problematic, and there isn’t much advantage to doing it that way.

Why not put the RAM under the working logics? Perhaps there is a practical way to layer reed cooling stuff between some of the logic/memory layers?

 

[theorist9]

I’m guessing they won’t use SoIC to stack CPU-die, and will instead put the RAM on top of the CPU (like they do for a bunch of their chips now). The cooling would be problematic, and there isn’t much advantage to doing it that way. Not unless they plan to re-do things so that, for example, one die is all CPU cores+cache, and another die is all GPU cores and neural.

Which Apple chips have the RAM stacked on top of the CPU? Are they all non-Mac chips? The teardowns I recall seeing of the AS Macs have the RAM to the side.

And could SoIC be used for RAM, or only to stack chips that TSMC makes itself?

 

[dada_dave]

Which Apple chips have the RAM stacked on top of the CPU? Are they all non-Mac chips? The teardowns I recall seeing of the AS Macs have the RAM to the side.

And could SoIC be used for RAM, or only to stack chips that TSMC makes itself?

I don’t know about a bunch but as @Jimmyjames shared supposedly the R1 in the Vision Pro has DRAM on chip.

 

[Cmaier]

Which Apple chips have the RAM stacked on top of the CPU? Are they all non-Mac chips? The teardowns I recall seeing of the AS Macs have the RAM to the side.

And could SoIC be used for RAM, or only to stack chips that TSMC makes itself?

The A-series have RAM stacked above the SOC.

SoIC could be used for anything, since it’s just a way to make via stacks.

 

[theorist9]

The A-series have RAM stacked above the SOC.

SoIC could be used for anything, since it’s just a way to make via stacks.

I was thinking specifically of TSMC's SoIC. I thought the concept behind TSMC-SoIC is not merely that the chips are stacked, but that connections extend from multiple points within the top chip to multiple points within the bottom chip (see depiction below), as opposed to just being connected on their edges, in order to provide shorter and faster links. And wouldn't such connections need to be built into the chips during manufacture? Thus in order to do this with DRAM, wouldn't TSMC need to manufacture DRAM (which I don't think they do)?

[I suppose it's possible TSMC could license its tech to a DRAM manufacturer, and have them make the RAM portion and ship it to TSMC, who then assembles the whole thing. But I don't know if that's practical, as opposed to assembling both chips together in an integrated manufacturing facility.]

https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC_inDepth.htm

 

[Cmaier]

I was thinking specifically of TSMC's SoIC. I thought the concept behind TSMC-SoIC is not merely that the chips are stacked, but that connections extend from multiple points within the top chip to multiple points within the bottom chip (see depiction below), as opposed to just being connected on their edges, in order to provide shorter and faster links. And wouldn't such connections need to be built into the chips during manufacture? Thus in order to do this with DRAM, wouldn't TSMC need to manufacture DRAM (which I don't think they do)?

[I suppose it's possible TSMC could license its tech to a DRAM manufacturer, and have them make the RAM portion and ship it to TSMC, who then assembles the whole thing. But I don't know if that's practical, as opposed to assembling both chips together in an integrated manufacturing facility.]

View attachment 30254

https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC_inDepth.htm

I don’t think that’s what that figure is intended to illustrate. What they are doing is comparing via structures. In “conventional 3D IC packaging” you have these wide contacts and you need them in order to align the visa. That means the pitch isn’t as good. Those “layers” you see in blue, above, aren’t chips. Those are dielectric layers between chips. The chips, laterally-speaking, would be on either side of those columns. The columns don’t go through the chips.