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theorist9

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I don’t think that’s what that figure is intended to illustrate. What they are doing is comparing via structures. In “conventional 3D IC packaging” you have these wide contacts and you need them in order to align the visa. That means the pitch isn’t as good. Those “layers” you see in blue, above, aren’t chips. Those are dielectric layers between chips. The chips, laterally-speaking, would be on either side of those columns. The columns don’t go through the chips.

View attachment 30255
Well, that's disappointing—then the tech is much less cool than I thought! I thought this would enable them to, for instance, have cache stacked directly on top of the CPU's, and vertically connected to the CPU's, thus significantly reducing the distance for signals sent between the two. I.e., like this:

1720254773041.png


The language they use to describe it is confusing (at least to me!). For instance, in:

M. -F. Chen, F. -C. Chen, W. -C. Chiou and D. C. H. Yu, "System on Integrated Chips (SoIC(TM) for 3D Heterogeneous Integration," 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, 2019, pp. 594-599, doi: 10.1109/ECTC.2019.00095.

...they descibe the the interconnects between the chips as being face-to-face: "In 3D stacking, chiplets are interconnected in face-to-face (F2F), face-to-back (F2B), and a combination of both." And their cartoons suggest that as well:
1720253108808.png


If the interconnects are not face-to-face, and are instead at the chip edges, then it seems the main advantage of stacking two chips is that they can be connected at all four edges instead of just one each, hence reducing the maximum communication distance between individual areas of the two chips. Is that what's going on?
 
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Cmaier

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Well, that's disappointing--then the tech is much less cool than I thought!

The language they use to describe it is confusing. For instance in:

M. -F. Chen, F. -C. Chen, W. -C. Chiou and D. C. H. Yu, "System on Integrated Chips (SoIC(TM) for 3D Heterogeneous Integration," 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, 2019, pp. 594-599, doi: 10.1109/ECTC.2019.00095.

...they descibe the the connections between the chips as being face-to-face: "In 3D stacking, chiplets are interconnected in face-to-face (F2F), face-to-back (F2B), and a combination of both." And their cartoons suggest that as well:
View attachment 30256

If the interconnects are not face-to-face, and are instead at the chip edges, then it seems the main advantage of stacking two chips is that they can be connected at all four edges instead of just one each, hence reducng the maximum communication distance between individual areas of the two chips. Is that what's going on?
Well, they are always face-to-face, when they are stacked. Even in the current packaging. What they don’t do iis go *through* a chip. Which means if two chips happen to talk, and they face each other, great. But if you need to talk to another chip above or below those two, you are going around them.

So those cartoons are showing going through multiple levels but NEXT to die. You aren’t going in the top of a die, through the die and out the bottom of the die. For that you are using interposers.
 

theorist9

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Well, they are always face-to-face, when they are stacked. Even in the current packaging. What they don’t do iis go *through* a chip. Which means if two chips happen to talk, and they face each other, great. But if you need to talk to another chip above or below those two, you are going around them.

So those cartoons are showing going through multiple levels but NEXT to die. You aren’t going in the top of a die, through the die and out the bottom of the die. For that you are using interposers.
But I'm not talking about when there's another chip above or below those two. I'm talking about if you have just two chips, like so. With TSMC-SoIC, are there not direct face-to-face signal connections between them?

1720255011794.png


I.e., isn't the bump density they're depicting here (from the article referenced above), which they describe in the text as the "interconnect I/O bonding density", the area density of F2F signal-carrying connections?

1720255804642.png
 
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Cmaier

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But I'm not talking about when there's another chip above or below those two. I'm talking about if you have just two chips, like so. With TSMC-SoIC, are there not direct face-to-face signal connections between them?

View attachment 30258

I.e., isn't the bump density they're depicting here (from the article referenced above), which they describe in the text as the "interconnect I/O bonding density", the area density of F2F signal-carrying connections?
yes, ypu can have i t like the above, but you could do that right now (and they do, albeit it not CPU->CPU. Right now it’s CPU->MOS capacitor, etc. Of course, you need the pins to line up if you want an image like that, and they never do. So, even today, it‘d be more like this (and that won’t change):

1720277901520.png


And the only difference i see in SoIC is how you align each layer - because you can align better, you don’t wide contacts on the chip surfaces.

1720277868885.png
 

Cmaier

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BTW, to make this more concrete, here, for example, is a public cross-section of A14. The other A-series chips look similar.

1720278837066.png


You can’t see much of the horizontal stuff, but nothing is a straight shot vertically. If we move the location of the cross-section to other slices, you’d see a lot of vertical connections off to the sides of the die, though some are vertical. And between the SoC die and the DRAM you can see some horizontal segments.
 

dada_dave

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BTW, to make this more concrete, here, for example, is a public cross-section of A14. The other A-series chips look similar.

View attachment 30265

You can’t see much of the horizontal stuff, but nothing is a straight shot vertically. If we move the location of the cross-section to other slices, you’d see a lot of vertical connections off to the sides of the die, though some are vertical. And between the SoC die and the DRAM you can see some horizontal segments.
I didn’t realize that the DRAM was stacked on top of the die in the A-series chip.
 

Cmaier

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I didn’t realize that the DRAM was stacked on top of the die in the A-series chip.
yep. that keeps the area of the package small enough to be practical for a phone form-factor. Downside, probably, is thermals.
 

B01L

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So talk at The Other Place has turned to P-core / E-core counts, and how Apple may go the route of more E-cores than P-cores for reduction of die space used and improved MT performance...?

With P-cores, only one (or a few...?) core can ramp up to maximum speed; but with E-cores, many can maintain their maximum speed...?

So, E-cores good for MT performance, maybe Apple goes the route of more E-cores than P-cores...?

Regarding a theoretical M4 Extreme SoC, the thought now seems to be 48P/16E cores, but maybe we get the opposite, 16P/48E cores; plenty of P-cores for multi-tasking with an assortment of single-core focused programs open, and a whole bunch of E-cores to crunch away on multi-threaded tasks...?

We also have the rumors of TSMC ramping up their 2nm process to get it ready for mass production in 2025, maybe this is when we see new Mac Studios, Mac Pros, and possibly the debut of the Mac Pro Cube; all with 2nm M5-series chips...

(..still reading through the thread on the 2nm ramp over there...)
 

Cmaier

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With P-cores, only one (or a few...?) core can ramp up to maximum speed; but with E-cores, many can maintain their maximum speed...
That’s not an inherent feature of P-cores. It’s a design choice. They chose a power curve and thermal design point and. max clock speed such that they can’t max the clock on all at once. But they could have, for example, declared a lower max clock speed and run them all, or done a million other things to allow all the P-cores to run at “max speed,” though that would bring different design tradeoffs.

A future design could easily allow all P-cores to run full out, if they make different design choices.
 

mr_roboto

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That’s not an inherent feature of P-cores. It’s a design choice. They chose a power curve and thermal design point and. max clock speed such that they can’t max the clock on all at once. But they could have, for example, declared a lower max clock speed and run them all, or done a million other things to allow all the P-cores to run at “max speed,” though that would bring different design tradeoffs.

A future design could easily allow all P-cores to run full out, if they make different design choices.
Agreed, though it's worth noting that Apple's shown us choices trending in the opposite direction. M1 started out very close to being able to maintain max clock speed on all P cores in a cluster; I think it was only about 5 or 6% penalty. M2 and M3 both have larger frequency reductions than that.

It's understandable that things are going that way since Apple has been adding more cores while keeping system power about the same.
 
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