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- Sep 26, 2021
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VLIW is a good way to lock yourself into a dead end, when it comes time to change the microarchitecture to improve performance and you end up having to either on-the-fly translate everything or recompile or whatever. You also give up a little bit because the compiler cannot take advantage of things that only are knowable at run-time (i.e. data-dependent pipeline holes, etc.), at least not without blowing up the instruction stream in size to handle every contingency. The complexity introduced by the scheduler, in the grand scheme of things, is not so huge that it’s worth the trade-off to get rid of it, at least not when you factor in that you need to recompile things every time you come out with a new chip with different characteristics.VLIW has been commercially implemented twice – by Intel and by Transmeta. The Intel version has been EoLed for several years now, being way too hot and not all tat impressive. The Transmeta design had some small amount of success, but not enough to keep them from going under.
My advisor was all over John Ellis’ work and I had some conversations with him about Bulldog many many years ago, but we didn’t go anywhere with it in my research group. I still have a bound copy of his dissertation sitting in my office, though.