Apple M6 rumors/discussion

[Cmaier]

I thought integrating the baseband is the obvious endgame. And why would they retain a separate RF chip? Is there a benefit (less RFI maybe) to keeping the RF chip far away from the processors? Because otherwise, maybe having it as a chiplet integrated in the SoC saves enough power to be interesting.

If by “separate” you mean “on a second die,” there are multiple reasons. First, process technologies for digital circuits are not ideal for analog circuits. So you tune the process differently for each (RF is inherently analog). It’s also typically a much larger node (for technical and cost reasons). And, yes, the RF section creates a lot of noise (inductive, near field, etc.) that will screw up the digital portions of the chip unless you shield them thoroughly. The digital portions of the chip can also screw up the analog portions, which are often quite sensitive!

Integrating it in the same SoC could make sense, but you will also want to keep the analog power supplies and any analog I/O far away from the digital power supplies and I/O; this could create practical problems in a chiplet-style package.

A typical CPU is a mix of analog (RAMs, clock PLLs, I/O drivers) and digital, but these typically have to work at CPU clock rates so we suck it up and work hard to keep things properly isolated. An entire RF chip would create a much more complicated noise profile that would be more difficult to cope with, and my understanding is that these circuits would be difficult to make very efficient and performative if running on a purely-digital tuned process.

 

[NotEntirelyConfused]

If by “separate” you mean “on a second die,” there are multiple reasons. First, process technologies for digital circuits are not ideal for analog circuits. So you tune the process differently for each (RF is inherently analog). It’s also typically a much larger node (for technical and cost reasons). And, yes, the RF section creates a lot of noise (inductive, near field, etc.) that will screw up the digital portions of the chip unless you shield them thoroughly. The digital portions of the chip can also screw up the analog portions, which are often quite sensitive!

Right, I understand all that. That's why I was talking about a separate RF chiplet being packaged with the processor chiplet, as opposed to integrating it directly on the same die as the CPU (and the baseband).

Integrating it in the same SoC could make sense, but you will also want to keep the analog power supplies and any analog I/O far away from the digital power supplies and I/O; this could create practical problems in a chiplet-style package.

This is the part where I'm completely ignorant. I don't know if that's a thing that takes careful design, or a thing that makes smart engineers go "yeah I quit, that's a guaranteed failure".

A typical CPU is a mix of analog (RAMs, clock PLLs, I/O drivers) and digital, but these typically have to work at CPU clock rates so we suck it up and work hard to keep things properly isolated. An entire RF chip would create a much more complicated noise profile that would be more difficult to cope with, and my understanding is that these circuits would be difficult to make very efficient and performative if running on a purely-digital tuned process.

Nobody was talking about doing it on the same process as the CPU (or at least I wasn't!).

So again, my question is, is that "much more complicated noise profile" something you have to be smart about when packaging with a CPU chiplet, or something you just never package with the CPU chiplet because it's just too hard (or not worth it)?

 

[throAU]

BTW, you'd likely see low-memory Max configurations with substantially less memory bandwidth, if memory I/O gets to 768 bits wide. You can't get chips small enough to fill all the channels with less than 48GB. They might reasonably drop channels for anything less than 72GB, even.

I don't see this as an issue?

If you're buying an M6 max in what... 2027-2028, buying less than 48GB for that machine is probably a stupid idea? Performance aside, you're crippling the machine to nickel and dime over a small percentage of the cost of just going to 96


edit:
yes, yes, current memory crisis aside...

 

[mr_roboto]

Another factor in keeping RF on a separate die is economics. RF analog transistors and standard cells are giant compared to digital. I am not an analog designer, but I've talked to them in the past, and IIRC it's something to do with self-noise - small transistors are inherently noisier than large. So, high performance radio frequency analog simply doesn't shrink as well as digital, not even the sort-of-analog circuits @Cmaier mentioned (such as SRAM). RF hit a scaling wall many years (and nodes) ago, and there's been little progress since.

This lack of scaling hasn't hurt because nobody's trying to fill reticle buster die with billions of RF transistors. But in turn, it also means most people building high performance RF chips just opt to make them in an older, cheaper node. Building them in a newer node doesn't make the size go down, and the newer node's wafers cost more, and it's more expensive to tape out chips. Why bother?

That said, there's something pushing in the opposite direction - lots of RF chips are really analog mixed signal, meaning there's some nontrivial digital blocks, in which case you'd like the digital stuff to be as small and low power as it can be. I suspect that's what's behind Apple's choice of TSMC 7nm for their C1 RF die. Once again, take with a grain of salt because I am far from a RF design expert, but as far as I know you don't need or want a node as new as 7nm for the analog RF circuits, but it'd help with any digital stuff.

 

[Cmaier]

Right, I understand all that. That's why I was talking about a separate RF chiplet being packaged with the processor chiplet, as opposed to integrating it directly on the same die as the CPU (and the baseband).


This is the part where I'm completely ignorant. I don't know if that's a thing that takes careful design, or a thing that makes smart engineers go "yeah I quit, that's a guaranteed failure".


Nobody was talking about doing it on the same process as the CPU (or at least I wasn't!).

So again, my question is, is that "much more complicated noise profile" something you have to be smart about when packaging with a CPU chiplet, or something you just never package with the CPU chiplet because it's just too hard (or not worth it)?

Almost anything is possible, but practically speaking you want to keep the RF chip far away from the logic chips. But far away means “far away in an electromagnetic sense”. So you can achieve this with physical distance or with shielding or other forms of isolation. The choice would boil down to cost/benefit. Are you really saving anything by putting them in the same package if you have to completely separate the package pins and surround all the wires with shields that take a lot of space?

 

[NotEntirelyConfused]

Almost anything is possible, but practically speaking you want to keep the RF chip far away from the logic chips. But far away means “far away in an electromagnetic sense”. So you can achieve this with physical distance or with shielding or other forms of isolation. The choice would boil down to cost/benefit. Are you really saving anything by putting them in the same package if you have to completely separate the package pins and surround all the wires with shields that take a lot of space?

Thank you for restating my question, better.

So, does anyone have anything approaching an answer to this? Or is it too dependent on the specifics of the chiplets involved, or of the packaging process that we don't know enough about yet?

 

[NotEntirelyConfused]

Another factor in keeping RF on a separate die

I thought I was super clear that I was talking about packaging different dies (dice?) together, not putting everything on one die. What I'm trying to understand better is what the possibilities are for packaging together things that would previously have been left discreet.

 

[Cmaier]

Thank you for restating my question, better.

So, does anyone have anything approaching an answer to this? Or is it too dependent on the specifics of the chiplets involved, or of the packaging process that we don't know enough about yet?

it’s too dependent on the process and the circuits. I’m confident it could be done, but whether the cost of doing so is worth it depends on too many unknown factors. I designed MCMs for my ph.d thesis, and you have to consider a lot of factors (power dissipation, power consumption, inductive coupling/cross-talk, physical constraints like dimensions, performance, etc.). That’s all engineering is - balancing all the constraints to find the best solution.