Apple M6 rumors/discussion

[rdrr]

I think it much more likely that Apple is having difficulty sourcing enough RAM than there are hordes of people clamoring to run openclaw.

Anyone here buying a Mac Mini and running openclaw?

 

[Nycturne]

Anyone here buying a Mac Mini and running openclaw?

I have a Mac Mini in my homelab, but it's to run Xcode builds.

Why run it myself when Meta's head of AI Safety AI Alignment can be the canary in the coal mine for me?

 

[dada_dave]

Apple MacBook Ultra with OLED touchscreen won't replace MacBook Pro, is said to be more expensive

Apple is set to launch a MacBook Pro with an OLED touchscreen, Face ID, a thinner chassis and a brand new design later this year. According to the latest rumors, this notebook could be marketed as a MacBook Ultra and not replace the MacBook Pro, but rather function as an even more expensive top...

www.notebookcheck.net

This report originates from Gurman, so take with a grain of salt, but it's possible

 

[Cmaier]

Apple MacBook Ultra with OLED touchscreen won't replace MacBook Pro, is said to be more expensive

Apple is set to launch a MacBook Pro with an OLED touchscreen, Face ID, a thinner chassis and a brand new design later this year. According to the latest rumors, this notebook could be marketed as a MacBook Ultra and not replace the MacBook Pro, but rather function as an even more expensive top...

www.notebookcheck.net

This report originates from Gurman, so take with a grain of salt, but it's possible

Even if they are creating a new tier above MBP, why wouldn’t they call it MacBook Studio instead of MacBook Ultra? Oh, I guess Studio is below Pro?

Maybe they rename the Pro Studio and name the new thing Pro.

Then pretend we all already own Studios.

 

[casperes1996]

Apple MacBook Ultra with OLED touchscreen won't replace MacBook Pro, is said to be more expensive

Apple is set to launch a MacBook Pro with an OLED touchscreen, Face ID, a thinner chassis and a brand new design later this year. According to the latest rumors, this notebook could be marketed as a MacBook Ultra and not replace the MacBook Pro, but rather function as an even more expensive top...

www.notebookcheck.net

This report originates from Gurman, so take with a grain of salt, but it's possible

It's also possible the exact decision on how to brand this device isn't nailed down yet. My money is on it just being a higher spec, higher priced product in the MacBook Pro line and the existing M5s keep the current price, but that it will just be sold as the higher spec MBP similar to what has been done a few times in the past.
But my money was also on the Neo just being called MacBook, so my track record with predictions is as poor as Gurman's

 

[casperes1996]

Even if they are creating a new tier above MBP, why wouldn’t they call it MacBook Studio instead of MacBook Ultra? Oh, I guess Studio is below Pro?

Maybe they rename the Pro Studio and name the new thing Pro.

Then pretend we all already own Studios.

Wouldn't that imply that Mac Studio (desktop) is a higher tier than Mac Pro (desktop)?.... Actually.... I guess that is also the case, given the Mac Pro still has M2 Ultra only...

 

[Cmaier]

Wouldn't that imply that Mac Studio (desktop) is a higher tier than Mac Pro (desktop)?.... Actually.... I guess that is also the case, given the Mac Pro still has M2 Ultra only...

well, as i said “oh, i guess studio is below pro” and hence they would rename all the existing products, like they did with the P and S cores.

Because I am being sarcastic.

 

[casperes1996]

well, as i said “oh, i guess studio is below pro” and hence they would rename all the existing products, like they did with the P and S cores.

Because I am being sarcastic.

I somehow missed all but the top paragraph in your prior post. Though my comment was also an attempt at a humorous dig at the Mac Pro anyway

 

[MerryCherry]

keep on eye on the A20 Pro in iPhone 18 Pro, the iPhone 18 should have at least 115.2GB/s memory bandwidth if they move to 6-channel as per Weibo leak.

6 channel (96 bit) LPDDR5X ?

Qualcomm / Mediatek are rumoured to be doing 4 channel (96 bit) LPDDR6.

What are the benefits of each approach?

 

[MerryCherry]

Any speculation for core count increases next gen?

A20 Pro = 2S+6E
A20 keeps 2S+4E

M6 = 6S+6E

M6 Pro/M6 Max = 8S+16P

On the GPU side we could see a core count increase due to;

- M6 will probably reuse the M5 GPU architecture (Family 10)
- Density improvement of N2

Possibly 20% increase (12/24/48 for M6/M6 Pro/M6 Max).

 

[dada_dave]

Any speculation for core count increases next gen?

A20 Pro = 2S+6E
A20 keeps 2S+4E

M6 = 6S+6E

M6 Pro/M6 Max = 8S+16P

On the GPU side we could see a core count increase due to;

- M6 will probably reuse the M5 GPU architecture (Family 10)
- Density improvement of N2

Possibly 20% increase (12/24/48 for M6/M6 Pro/M6 Max).

Based on my M5 GPU analysis published in the M5 thread, as impressive as the M5 is, I really do hope they add at least a couple of GPU cores to the base M6:

View attachment 38308

Base M5 GPU analysis: This comes from NotebookCheck running CP2077 (now native to macOS) with load-only power (i.e. load - idle). As we can see, the M5 is a massive upgrade over the M4 in the MB Air, however performance increases quickly diminish with increasing power. While the 10-core M5 in the 14" MBP is by no means inefficient, it can't keep up with the larger B390 with its 2 extra cores in terms of performance/efficiency. Of course, as discussed in the Panther Lake-H analysis, that chip straddles the base-Pro divide for Apple processors and no processor measured even attempts to operate in the power regime of the Air (again which loses far less performance than you might think). The 10-core M5 is only 15% more performant than the 8-core while using 25% more power. at first glance this might be surprising, but I've noticed this pattern throughout Apple's GPUs across different levels where the binned GPU performs much better than expected (or conversely the full GPU performs worse than expected). Part of it may be that memory bandwidth isn't always binned, but if memory serves this appears to be true even when it is.

 

[NotEntirelyConfused]

6 channel (96 bit) LPDDR5X ?

Qualcomm / Mediatek are rumoured to be doing 4 channel (96 bit) LPDDR6.

What are the benefits of each approach?

I can't imagine Apple doing 16-bit channels on LPDDR6. Aside from the ick factor, I would be surprised if such memory were widely available. It would likely cut their sourcing options way too much when that's already a huge problem to solve.

The only benefit of going with 16-bit channels I know of is the small energy savings, as you wouldn't be paying to move around the extra 32 bits per 256 used for ECC. That's 12.5% of your total cost for moving data between RAM and CPU, plus the cost of running the ECC engines. But you'd lose the ECC, and I think they won't make that choice, even if supply constraints are somehow not a factor.

 

[mr_roboto]

I can't imagine Apple doing 16-bit channels on LPDDR6. Aside from the ick factor, I would be surprised if such memory were widely available. It would likely cut their sourcing options way too much when that's already a huge problem to solve.

The only benefit of going with 16-bit channels I know of is the small energy savings, as you wouldn't be paying to move around the extra 32 bits per 256 used for ECC. That's 12.5% of your total cost for moving data between RAM and CPU, plus the cost of running the ECC engines. But you'd lose the ECC, and I think they won't make that choice, even if supply constraints are somehow not a factor.

16-bit channels are the normal (maybe only? Not sure) option for LPDDR5, and they aren't icky at all.

They're a performance feature, rather than an efficiency feature. For a given total DDR interface width, splitting it into more channels gives you more command parallelism and more total open DRAM pages. Both of these are important for memory performance in complex SoCs with lots of agents generating memory traffic. Since LPDDRn originated as a standard for phone SoCs where the path to DRAM usually isn't more than 64 bits, you need narrow channels if you want more memory parallelism. Apple kept using it with M-series chips because lots of channels is a really good thing for desktop class performance, too.

 

[casperes1996]

Any speculation for core count increases next gen?

A20 Pro = 2S+6E
A20 keeps 2S+4E

M6 = 6S+6E

M6 Pro/M6 Max = 8S+16P

On the GPU side we could see a core count increase due to;

- M6 will probably reuse the M5 GPU architecture (Family 10)
- Density improvement of N2

Possibly 20% increase (12/24/48 for M6/M6 Pro/M6 Max).

This sounds nice but do you really think they'd bump both CPU and GPU core count at the same time?

Even going to a new node, I would expect them to only bump one or the other - My money is on GPU this time. Though it is possible that they'll bump both if the new "Fusion Architecture" and moving from mostly P cores to mostly E cores on the Pro and Max give enough space savings even with more cores that they'll bump both.

 

[leman]

This sounds nice but do you really think they'd bump both CPU and GPU core count at the same time?

Even going to a new node, I would expect them to only bump one or the other - My money is on GPU this time. Though it is possible that they'll bump both if the new "Fusion Architecture" and moving from mostly P cores to mostly E cores on the Pro and Max give enough space savings even with more cores that they'll bump both.

I’ve seen this comment on RTW

You're right. I didn't realize there is such a small density improvement from N3P to N2. Even A16, with backside power, is only a 10% density improvement over N2P. Since density improvements are slowing down, total silicon area will have to grow.

If this is accurate, Apple going chiplet route already now makes perfect sense. Monolithic solutions are becoming non-viable.

 

[NotEntirelyConfused]

16-bit channels are the normal (maybe only? Not sure) option for LPDDR5, and they aren't icky at all.

They're a performance feature, rather than an efficiency feature. For a given total DDR interface width, splitting it into more channels gives you more command parallelism and more total open DRAM pages. Both of these are important for memory performance in complex SoCs with lots of agents generating memory traffic. Since LPDDRn originated as a standard for phone SoCs where the path to DRAM usually isn't more than 64 bits, you need narrow channels if you want more memory parallelism. Apple kept using it with M-series chips because lots of channels is a really good thing for desktop class performance, too.

I'm aware of all this. But LPDDR6 is different.

Standard LPDDR6 has 24-bit-wide channels, which are really two (mostly?) independent 12-bit subchannels. With a 50% longer burst length, which is generally compensated for by the faster clocks, you get 288 bit transfers per subchannel, of which 32 are for ECC (or other) purposes. You can shut down one subchannel to save power.

Apparently, at least one memory mfg is making a variant with 16-bit width. I'm not clear on how that's LPDDR6 then as you're giving up a lot to make something that's more like faster LPDDR5X but I haven't really paid much attention to this. That's the "ick" - you lose all the nice things you get with LPDDR6 except some speed. And in fact, now that I think about it, you probably won't even save (much?) on power as you won't be able to use the single-subchannel feature.

I really don't see Apple doing 16-bit. In fact, the most obvious thing for them to do it simply use the new channel width. That gives you 1.5 * 8/9 = 33% more bandwidth iso-clock. And of course clocks are going up too, so that's a significant bump up.

 

[NotEntirelyConfused]

I was thinking about just how much room they have to bump core counts with the new chiplet design.

One of the things we still don't know is how the non-CPU/GPU elements of the chip are distributed. They could have put just the GPUs and memory controllers on the GPU chiplet. That's sort of the obvious thing to do. But it's not the only choice. I could imagine them putting video encode/decode there too - and I bet they did. I could imagine the ISP going there, because it wants plenty of BW to memory, though it's not latency-sensitive (if that's even an issue) so maybe not. The SE is likely with the CPUs. But display controllers could be with the GPUs- the Max supports more than Pro. And maybe you want those near the TB5 controllers?

Point is, there may be a LOT of room for the CPU die to grow. And somewhat less for the GPU than many people think.

 

[Cmaier]

I was thinking about just how much room they have to bump core counts with the new chiplet design.

One of the things we still don't know is how the non-CPU/GPU elements of the chip are distributed. They could have put just the GPUs and memory controllers on the GPU chiplet. That's sort of the obvious thing to do. But it's not the only choice. I could imagine them putting video encode/decode there too - and I bet they did. I could imagine the ISP going there, because it wants plenty of BW to memory, though it's not latency-sensitive (if that's even an issue) so maybe not. The SE is likely with the CPUs. But display controllers could be with the GPUs- the Max supports more than Pro. And maybe you want those near the TB5 controllers?

Point is, there may be a LOT of room for the CPU die to grow. And somewhat less for the GPU than many people think.

In addition to the possibility of growing the die, they could just use more of them.

 

[NotEntirelyConfused]

In addition to the possibility of growing the die, they could just use more of them.

Of course, and if they ever release an Ultra++ that will presumably be what they do. An Ultra could easily be 3 or 4 chiplets. But to hit the Pro and Max prices, they're not likely to increase silicon spending all that much, so it seems unlikely they'd go for more chiplets (unless there's some significant advantage other than raw cost of silicon, which comes back to what I posted a couple days ago).

 

[casperes1996]

Of course, and if they ever release an Ultra++ that will presumably be what they do. An Ultra could easily be 3 or 4 chiplets. But to hit the Pro and Max prices, they're not likely to increase silicon spending all that much, so it seems unlikely they'd go for more chiplets (unless there's some significant advantage other than raw cost of silicon, which comes back to what I posted a couple days ago).

I agree, but at the same time, they could potentially use more silicon, if the defect rate can be lowered this way