NotEntirelyConfused
Power User
- Joined
- May 15, 2024
- Posts
- 167
Shockingly, we don't seem to have a thread for this yet, so let me start off with this.
[Note: Edited later because I was dumb and referred to channels when I was counting 64-bit paths, which is relevant neither to LPDDR5 nor recent Apple Silicon chips, which all use LPDDR5. Sad thing is I knew that already and was just being lazy.]
As I understand it, WMCM (as rumored to be used by future Apple chips like the A20 and M6), connects dies top-to-bottom, which means that shoreline (aka beachfront) is no longer a limiting factor for off-die IO, though lots of TSVs will presumably put some pressure on yield.
Therefore, using WMCM, Apple can use wider memory busses than previously practical. However this is limited at the low end by the number of RAM dies they want to use- they have to have a sufficiently low memory config for their baseline product, and nobody thinks they're going to go to, say, 24GB minimum during the RAM supply crunch. So if Apple is consistent with past lineups, we're likely to see 192 bits wide memory on the base M6 (18GB minimum), 384 on the Pro (24 or 36GB minimum, depending on whether they use 4 or 6GB chips), 768 on the Max, and 1536 (!!) on the Ultra, if they ship that chip.
Of course it's possible they could go to 256 bits wide for the base chip, and only populate 192 of them for the base memory config, but that seems somewhat unlikely. Though perhaps not totally - the memory controllers are not wedded to individual CPU complexes, as they are with certain other architectures, so you wouldn't get totally unbalanced performance from some CPUs or GPUs because of the idle controller.
Channels will obviously still be limited by SoC layout - you need to put the memory near the memory controllers on the SoC- but 768 bits wide on a Max die should easily be practical, as memory dies do not have to sit entirely within the footprint of the SoC die.
Is this correct or am I missing something?
[Note: Edited later because I was dumb and referred to channels when I was counting 64-bit paths, which is relevant neither to LPDDR5 nor recent Apple Silicon chips, which all use LPDDR5. Sad thing is I knew that already and was just being lazy.]
As I understand it, WMCM (as rumored to be used by future Apple chips like the A20 and M6), connects dies top-to-bottom, which means that shoreline (aka beachfront) is no longer a limiting factor for off-die IO, though lots of TSVs will presumably put some pressure on yield.
Therefore, using WMCM, Apple can use wider memory busses than previously practical. However this is limited at the low end by the number of RAM dies they want to use- they have to have a sufficiently low memory config for their baseline product, and nobody thinks they're going to go to, say, 24GB minimum during the RAM supply crunch. So if Apple is consistent with past lineups, we're likely to see 192 bits wide memory on the base M6 (18GB minimum), 384 on the Pro (24 or 36GB minimum, depending on whether they use 4 or 6GB chips), 768 on the Max, and 1536 (!!) on the Ultra, if they ship that chip.
Of course it's possible they could go to 256 bits wide for the base chip, and only populate 192 of them for the base memory config, but that seems somewhat unlikely. Though perhaps not totally - the memory controllers are not wedded to individual CPU complexes, as they are with certain other architectures, so you wouldn't get totally unbalanced performance from some CPUs or GPUs because of the idle controller.
Channels will obviously still be limited by SoC layout - you need to put the memory near the memory controllers on the SoC- but 768 bits wide on a Max die should easily be practical, as memory dies do not have to sit entirely within the footprint of the SoC die.
Is this correct or am I missing something?
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