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One port is USB 3, and the other is USB 2. I’d bet money you can’t use both at their maximum throughput.
And none of this has anything to do with apple fabric, I’m sure.
MacBook Neo is the Chosen One
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One port is USB 3, and the other is USB 2. I’d bet money you can’t use both at their maximum throughput.
And none of this has anything to do with apple fabric, I’m sure.
Apple fabric is the custom interface between ports and associated, is it not? https://discussions.apple.com/thread/254919696
If you can use both ports at maximum throughput, what would that likely signal?
I've only seen the term "Apple Fabric" used in connection with the SSD. It could also refer to the on-chip network. Neither of these usages of the term have anything to do with USB ports. You need to connect the USB controller somewhere. The A18 has only one USB controller, and it's not feasible to add another one inside the SoC. So they went for the quick and dirty solution and placed a cheap hub in front of their "real" USB port.
Isn't PCIe bus generally how a chip connects to the rest of the board, yes for the SSD, but also to ports? That's what I'm assuming Apple fabric is. Nonstandard bus for the chip. Im genuinely asking. I'm trying to learn more than what I know
I'm saying this to mean if it has limited connections internally then it's not even possible to have 2 USB 3 ports without compromise. If this is the case, how does this affect their decision and engineering effort in adding a second port.
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Problem is that hub, it looks like, won’t support the USB 3.0 speeds needed for the fast port (at least not according to the documentation I found on-line). So I’m still not sure exactly what they are doing.
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That something magical is going on. There’s no possible way to do it without them having modified the SoC die, afaik.
USB 3 ports have two (type A) or four (type C) high speed diff pairs to support SERDES based links like USB 3.0, DP alt mode, or Thunderbolt. They also have a single USB2 diff pair. If you plug in a USB2 device, it only connects to the dedicated USB2 pair.
So, every full featured USB type C port is two different USB ports in one trenchcoat. Seems like they've put a 2.0 hub in front of A18 Pro's single 2.0 controller, splitting it for the two ports, but provided no hub for the 3.0 signals.
Why they didn't hubify the 3.0 signals, I don't know, but probably something along the lines of "it would be bad if DP alt mode forced the second port to suddenly be USB2 only". I don't know enough of the gory details here to be sure. In fact, I thought I'd read about things which might prevent what they did do, so it interests me that they pulled it off, with an off the shelf 2.0 hub IC, but probably whatever shenanigans there are can be done in firmware and drivers.
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Ah, so they are using two ports on the hub to send two USB 2.0 signal pairs to the two external ports, and then they send 4 differential pairs (from the SoC’s USB controller) to just the USB 3.0 external port? Makes sense.
In the PC world, that is indeed a standard approach - use a universal bus (PCIe) and connect different controllers and devices to it. However, that’s not what Apple does. Their design goal is saving power and die space by providing exactly what’s needed for the product. In that sense, there is no „customizable bus“ as such. I think the „fabric“ you are talking about is just a dedicated link to the SSD, nothing more.
So does this Fabric connect USB/ Thunderbolt? I'm confused.
Explainer: chipsets and Fabric
From the IBM PC XT with its 10 MB hard disk to a SoC which moves data to its SSD at over 7 GB/s. How CPUs interface with peripherals.
eclecticlight.co
So does this Fabric connect USB/ Thunderbolt? I'm confused.
Explainer: chipsets and Fabric
From the IBM PC XT with its 10 MB hard disk to a SoC which moves data to its SSD at over 7 GB/s. How CPUs interface with peripherals.
My understanding is that USB/Thunderbolt controllers are inside the SoC and that the SoC is more or less directly wired to the ports. I am not aware of a universal external bus on Apple Silicon. I might be mistaken however.
IMO, the difficulty is because Fabric is not really a technical term, but more of a marketing one. It seems to me when Howard talks about Fabric he means all the I/O integrated into a SoC.
It's not a marketing term at all - it's a common engineering term for something sort of akin to a network switch or router, whose ports implement some kind of bus standard.
Here's an example. Never heard of this company before, it's just the first search hit I saw for "axi fabric". AXI is an Arm Holdings bus standard; it's the bus interface most Arm CPU IP complexes (core(s) + caches) present to the world. Lots of low to medium performance Arm-based SoCs are built on nothing but AXI fabrics.
In a higher performance SoC (like Apple Silicon) you might have AXI at some edges of the internal network-on-chip (NoC) that connects everything together, because there are going to be peripherals (or even CPUs) which speak AXI. However, the main internal NoC backbone or "fabric" will be something optimized for better area, wire count, power, throughput, or latency than plain AXI. "Apple Fabric" is just Apple's name for their presumably fully custom main NoC fabric. There are also IP vendors out there who will sell you the equivalent if you want to build your own SoC; was sniffing around for jobs at one of those companies once, but didn't end up applying.
That just reminded me of the iPhone 5/5s design losing its shiny diamond-cut chamfered edge when it became the iPhone SE. I guess it's a fair amount of extra cost for the shiny.
@Cmaier @mr_roboto
And anyone else who wants to contribute.
There is a new video out with a high resolution close up of the logic board. Can you contribute your expertise to hypothesize what they did to add a second USB C port? I'd love to hear it! Thanks
The logic board is so tiny. I have long been wondering about a cheap "Mac Micro" using the iPhone chipset and the Apple TV-like case and we might need even less room than the Apple TV.
Just for fun, here's the NBC data for the Neo:
The Neo is currently the fastest ST non-Apple laptop chip on the market - it even edges out the M3 - with an efficiency (>24pts/W) better than anyone else ... by a lot, even compared to other Apple devices. I have loaded up the Neo's CB24 MT and CP2077 but the graphs, especially the MT one, needs some cleaning. Basically yeah it isn't winning any GPU or MT CPU drag races, but especially for the MT it's incredibly efficient at 57 pts/W and it still gets the performance (416 pts) of a Lunar Lake chip set at the power levels where Intel loves to make grandiose claims about amazing battery life and the A18Pro still trounces that Lunar Lake chip in efficiency (~2.5x more efficient). For CP2077 at 1080p Ultra, I mean obviously it's not playable at 5.6 FPS, but it retains the basic efficiency of the M4 generation of about 0.72FPS/W and only sips less than 8W. Though some higher end games will be playable, GPU is geared towards lighter games. But for a device like this that ST score and efficiency rating is really the important one.
The Neo is currently the fastest ST non-Apple laptop chip on the market - it even edges out the M3 - with an efficiency (>24pts/W) better than anyone else ... by a lot, even compared to other Apple devices. I have loaded up the Neo's CB24 MT and CP2077 but the graphs, especially the MT one, needs some cleaning. Basically yeah it isn't winning any GPU or MT CPU drag races, but especially for the MT it's incredibly efficient at 57 pts/W and it still gets the performance (416 pts) of a Lunar Lake chip set at the power levels where Intel loves to make grandiose claims about amazing battery life and the A18Pro still trounces that Lunar Lake chip in efficiency (~2.5x more efficient). For CP2077 at 1080p Ultra, I mean obviously it's not playable at 5.6 FPS, but it retains the basic efficiency of the M4 generation of about 0.72FPS/W and only sips less than 8W. Though some higher end games will be playable, GPU is geared towards lighter games. But for a device like this that ST score and efficiency rating is really the important one.
Oh, absolutely. What I mean is that “Apple Fabric” does not let us infer anything about the topology, performance, or other properties, unlike, say “NVLink” or “FSB”. In particular, Howard could be talking about “on-chip I/O controllers” or “integrated controllers” instead of “Fabric” with zero loss of information. If we are talking about the on-chip network, we do know quite a lot from Apple patents, but that to has little to do with external I/O.
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I’d like to add that shared bandwidth between usb3 and 2 hardly matters. USB 2 is 480Mbps. USB3.1 Gen 1 is 5Gbps. Gen 2 is 10Gbps. I don’t believe it supports 2x2 at 20Gbps. But if we assume a 3.1 gen 2 device going af 10Gbps, I don’t think it matters too much if a full load is put on the USB2 port, taking the usb3 port down to 9.52Gbps. It’s hardly a big difference.