X86 vs. Arm

[Yoused]

When I look at the wikithingy article on "microcode", it comports with my understanding of the term. It is at the heart of the RISC concept: processors had little internal programs that implemented the elaborate ISAs of earlier processors, but analysis revealed that compilers were eschewing many of the complex instructions in favor of the more basic ones, leaving much of the architecture largely unused. RISC simply pulled the function of the processor out of the internal microcode and put it into the ISA, leaving more room in the core for things like more registers.

I suspect that an op like udiv on an 8086 or 68000 was basically the simple program that would be written in software, distilled down into microcode, which would execute much faster primarily because there would be no code fetching, but it was still a lot like what one would write by hand. Of course, udiv is not a frequently-used op, but it still took up space in the processor core (ARM32 never had dedicated division ops). The microcode design gave engineers a simple way to make modifications to the processor, but when RISC came along and started pantsing the older processor designs, they had to switch to the micro-op structure to keep up. Pentium was the first x86 processor to almost completely ditch the microcoded design pattern.

 

[mr_roboto]

I suspect that an op like udiv on an 8086 or 68000 was basically the simple program that would be written in software, distilled down into microcode, which would execute much faster primarily because there would be no code fetching, but it was still a lot like what one would write by hand. Of course, udiv is not a frequently-used op, but it still took up space in the processor core (ARM32 never had dedicated division ops). The microcode design gave engineers a simple way to make modifications to the processor, but when RISC came along and started pantsing the older processor designs, they had to switch to the micro-op structure to keep up. Pentium was the first x86 processor to almost completely ditch the microcoded design pattern.

Pentium Pro was the first x86 to poularize the term "micro ops". More to the point, as @Cmaier said, micro ops are just a different name for microcode. It's a distinction without a difference; x86 chips never stopped being microcoded.

 

[leman]

My understanding has always been that “micro ops” is whatever comes out of the decoder while “microcode” are internal programs used to implement more complex or situational instructions.

Interestingly enough, some ARM designs used to have micro op caches until recently. From what I’ve read Apple never used micro op caches, but they describe some instructions as “microcoded” (for example complex table lookup).

 

[dada_dave]

*e.g. Arrow Lake's gaming performance relative to AMD and even its own older chips is for some reason, head scratchingly bad, despite its productivity gains - seriously no one can figure it out as far as I can see as with better single thread and no SMT gaming should be better

I was wrong, people do have theories:

Intel Panther Lake will allegedly reintegrate the memory controller into the compute tile — Nova Lake is expected to separate the two again with added optimizations

Can Intel address its inherent latency issues in Arrow Lake with Nova Lake?

www.tomshardware.com

Apparently Arrow Lake separated its memory controller onto a different die and with a slower than normal ring bus, latencies are really bad. Pretty sure Zen 2 or 3 or both did something similar (separate IO die, not ring bus) but I guess the infinity fabric is good enough that it didn’t really affect Zen as much? Regardless this seems to be the prevailing theory on why Arrow Lake gaming is so underwhelming.