Intel Raptor Lake

[Citysnaps]

For these sorts of things the fab always assembles a reticle by combining sub-reticle masks. As a grad student I used to get discounted fab access by keeping my projects small enough to fit in odd spaces the fab told us were available. I assume it works the same way with tsmc. (Minus the discount)

Thanks... Happen to recollect what percentage of a wafer you got and the price?

 

[Cmaier]

Thanks... Happen to recollect what percentage of a wafer you got and the price?

Nope. Small small percentage.

 

[Citysnaps]

Nope. Small small percentage.

Thanks… I’m trying to wrap my head around the mechanics relative to what was done at our fab. Please bear with me.

“For these sorts of things the fab always assembles a reticle by combining sub-reticle masks.”

Does that mean “a reticle” is simply some number of sub-reticles from multiple customers (including your project) that get serial loaded as the wafer is being stepped (repeating each layer).

Or… that sub-reticles are assembled into a single mask/reticle that is exposed over the entire wafer, for each layer?

 

[Cmaier]

Thanks… I’m trying to wrap my head around the mechanics relative to what was done at our fab. Please bear with me.

“For these sorts of things the fab always assembles a reticle by combining sub-reticle masks.”

Does that mean “a reticle” is simply some number of sub-reticles from multiple customers (including your project) that get serial loaded as the wafer is being stepped (repeating each layer).

Or… that sub-reticles are assembled into a single mask/reticle that is exposed over the entire wafer, for each layer?

I’m not sure it’s either, if I understand your question.

In this situation, I create a mask set with some fixed dimensions. Say 1mm x 1mm. My origin is (0,0). By “mask set” I mean I create a gds file which contains the necessary geometry on every layer.

I send that to the fab, which has also received similar mask sets from other customers. The fab assembles each mask set into a single reticle mask set by simply changing the offset of each of our mask sets.

So now they have a single reticle set (a reticle for each layer) that includes all the different projects on it. They then step that reticle across the entire wafer, one layer at a time.

 

[Citysnaps]

I’m not sure it’s either, if I understand your question.

In this situation, I create a mask set with some fixed dimensions. Say 1mm x 1mm. My origin is (0,0). By “mask set” I mean I create a gds file which contains the necessary geometry on every layer.

I send that to the fab, which has also received similar mask sets from other customers. The fab assembles each mask set into a single reticle mask set by simply changing the offset of each of our mask sets.

So now they have a single reticle set (a reticle for each layer) that includes all the different projects on it. They then step that reticle across the entire wafer, one layer at a time.

OK, got it, thanks. Reading what I wrote previously, it seems to be a hybrid of the two options I speculated (and really know little) about.

 

[Yoused]

OK, got it, thanks. Reading what I wrote previously, it seems to be a hybrid of the two options I speculated (and really know little) about.

Picture you are building a house with a powerful laser. You set down the floor and put a 2' tall block of material on it. The first mask is the base pattern of the walls: the laser evaporates all the space between the walls (and some conduit troughs inside the walls). Then you lay down the next 3' block of material and use the next mask, which is ery similar but slightly different because it has window gaps, and burn away more interior space. The mask for the third 2' block differs in that it blocks evaporating the tops of door frames.

A chip has dfferent layers in a sorta analogous way: a single reticle is several layer masks, for burning off gate, insulator and wiring patterns. Some chips have many layers of wires. And they do this with picometer precision.

 

[Citysnaps]

Picture you are building a house with a powerful laser. You set down the floor and put a 2' tall block of material on it. The first mask is the base pattern of the walls: the laser evaporates all the space between the walls (and some conduit troughs inside the walls). Then you lay down the next 3' block of material and use the next mask, which is ery similar but slightly different because it has window gaps, and burn away more interior space. The mask for the third 2' block differs in that it blocks evaporating the tops of door frames.

A chip has dfferent layers in a sorta analogous way: a single reticle is several layer masks, for burning off gate, insulator and wiring patterns. Some chips have many layers of wires. And they do this with picometer precision.

Thanks. My curiosity was more about how small company runs/proto runs/university runs/research/experiments/etc were co-mingled with regular production runs; and speculating how that might be managed.

I came from a world where the five person company I worked for (we designed, marketed, and sold full-custom CMOS special purpose signal processing ASICs. We used a foundry (European Silicon Structures - ES2 in Provence, France) whose business model was based upon using e-beam lithography and being able to routinely handle/co-mingle multiple different kinds of runs. We called them zebras - getting a slice of a wafer along with other companies.

The economics were great for us as our volumes were not huge (compared to a regular semiconductor company) and the costs/turnaround were decent. In the mid-late ‘90s ES2 was acquired by Atmel in San Jose, California.

Reading up above that TSMC had their shuttle service piqued my curiosity. And was wondering if what we did long ago was viable today using that service. Trying to put it all in perspective.

 

[mr_roboto]

For these sorts of things the fab always assembles a reticle by combining sub-reticle masks. As a grad student I used to get discounted fab access by keeping my projects small enough to fit in odd spaces the fab told us were available. I assume it works the same way with tsmc. (Minus the discount)

Yeah, I don't think you get to put reticle buster chips through TSMC shuttle runs, they need to combine a bunch of smaller masks to make the economics work.

 

[theorist9]

13900KS review:

Intel Core i9-13900KS Review: The World's First 6 GHz 320W CPU

The fastest and most power hungry PC chip ever.

www.tomshardware.com

And GB5 scores. These are some of the higher ones, but there are a few in this range, suggesting these are the ones done with good cooling....

....as opposed to this, which may be an outlier. Though it does specify faster RAM (4104 MHZ).

 

[Colstan]

13900KS review:

I saw the Hardware Unboxed review two weeks ago, but didn't post it, because it didn't seem worth mentioning. The gains aren't noticeable and the power consumption is through the rough. Gelsinger was showing it off on stage, assuming that it would take on AMD's 3D V-Cache models. Since Intel didn't send out review samples, and Hardware Unboxed had to get their 13900KS elsewhere, I assume that Intel is trying to avoid advertising it. They released it, it's notable for being 6Ghz, but that battle ended long ago. Whether it is with this chip or Arc, Intel is constantly fighting battles of yesteryear.

 

[Cmaier]

I saw the Hardware Unboxed review two weeks ago, but didn't post it, because it didn't seem worth mentioning. The gains aren't noticeable and the power consumption is through the rough. Gelsinger was showing it off on stage, assuming that it would take on AMD's 3D V-Cache models. Since Intel didn't send out review samples, and Hardware Unboxed had to get their 13900KS elsewhere, I assume that Intel is trying to avoid advertising it. They released it, it's notable for being 6Ghz, but that battle ended long ago. Whether it is with this chip or Arc, Intel is constantly fighting battles of yesteryear.

I still remember when we had to put numbers on our chips that looked like clock speeds but weren’t, because our IPC was higher than Intel but people just bought whichever chip had the most megahertz.

 

[Colstan]

I still remember when we had to put numbers on our chips that looked like clock speeds but weren’t, because our IPC was higher than Intel but people just bought whichever chip had the most megahertz.

My second AMD CPU was a 2.2Ghz Athlon XP 3200+. I had a lot of fun tweaking it. I didn't have a lot of fun replacing it, after I killed it with too much voltage.

My first AMD CPU would have been a 133Mhz 5x86, which I also overclocked the hell out of, but it didn't give up the ghost on me.

These days, overclocking just ain't worth it.

 

[theorist9]

I still remember when we had to put numbers on our chips that looked like clock speeds but weren’t, because our IPC was higher than Intel but people just bought whichever chip had the most megahertz.

During that time, did anyone ever argue for marketing heavily based on IPS (instructions per second)? The 2000 Athlon, for instance, was 3.6 GIPS at 1.2 GHz, and "3.6 billion instructions per second" sounds more impressive than "1.2 GHz".

Instructions per second - Wikipedia

en.wikipedia.org

 

[Cmaier]

During that time, did anyone ever argue for marketing heavily based on IPS (instructions per second)? The 2000 Athlon, for instance, was 3.6 GIPS at 1.2 GHz, and "3.6 billion instructions per second" sounds more impressive than "1.2 GHz".

Instructions per second - Wikipedia

en.wikipedia.org

I had no interactions with marketing, thankfully