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I know little to nothing about this, but given their track record so far I can easily believe Tom’s is misapprehending what a TSMC engineer actually said. That said, TSMC does seem to suggest that A16 might only be viable for larger chips “with dense power delivery networks”. Which I’ll be honest I’m not sure what that means for its use in Apple products, but it doesn’t sound conducive for building A/M chips.
i think the issue is
(1) it costs more, so you aren’t going to do it unless you really need to do it
(2) the vias through the silicon may be fairly large (i would guess they might approach the size of a standard cell), so you have to be able to accommodate that
(3) backside power delivery isn’t all that helpful unless your current density is so high that power rails on M1-M3 would limit routing channels for signals. That doesn’t happen for most circuits, not even for most parts of CPUs.
I don’t think backside power delivery lets you get rid of the M1 VSS/VDD in each standard cell row - the vias are likely to just be too big - even if they are a fraction of the size I think they are - so your savings are on M2 and M3 (and M4 and up, but most signals are routed on M1-M3, and there’s rarely much routing congestion above M3).
I’d love to see a stack up or design rules, though. Maybe TSMC has something planned that is completely different than how I think it would work.