M5 Pro and Max unveiled

[dada_dave]

Only reason I could see for that changing is if the Super core was *a lot* more power hungry, but it's the same as what we used to call P in the base M5, so we know for a fact it's not an unreasonably power hungry core that would make it infeasible to rely on it for most tasks

Agreed! But this line of logic is why I thought they wouldn't go with a Middle Core and they did! I'm not saying my "thread scheduling change to take advantage of the new core type" hypothesis is right either btw, I'm also a fan of the "un-core efficiency improvements" hypothesis. But the former is possible.

 

[RockRock8]

Again, you are appear to be confusing the computational demands of different workloads. The battery life improvement has been quoted for workloads where over 95% of the CPU time is spent waiting in a low-power mode, and where most cores are powered down. The power consumption of such workloads is dominated by the baseline power and other involved IP blocks - memory, caches, data busses, networking components etc. That’s what “uncore” refers to.

I am not conflating anything. I'm literally just comparing the fact that the Max chip gets objectively less battery life even in light usage than the Pro chip. Changing the core configuration of the Max chip to use less HP cores is going to help battery life generally speaking. And it did. If they chose to do so without creating a third type of core, you'd also get a side grade in performance for CPU like M3 Pro did, but they didn't, so now you get 15% increased multi threaded performance overall M5 Max vs M4 max

 

[RockRock8]

I don't think anyone is disputing that this new core type will change how Apple designs SOCs ... it already has ... or that this isn't a big deal ... it is very much so

Due respect, half this thread is about the name change, so forgive me, but up until the last 4 posts most of it hasn't been focused on what the implications are now and for other chips lol.

I think the misapprehension you are under is that the battery life tests are multi-core?

I'd like you to show the M4 Max and M4 Pro gets the same battery life on light tasks, using official or unofficial metrics. Until then I don't know why you're saying that. I don't have any misapprehension that streaming is a hardware accelerated light task on M chips lol.

 

[RockRock8]

It’s not ganging up just because we disagree. I promise you none of us are coordinating our responses in any way. In fact, us four don’t even seem to be addressing the same points (though there appears to be some overlap).

I don’t think we are ganging up on you at all, in fact I think it’s a very civil and constructive conversation. You can take as much time as you need to respond too, this is not a synchronous medium. Just something to think about, if you have multiple people (all experts in their own right) challenging your argument, maybe it’s a good time to reanalyze your premises?

To clarify, I should have used the word "pile on," because I wasn't trying to say it was some conspiracy, so im sorry if it came across negatively like that, but let's be real also: all 4 of you disagreed with me in some way or another for the last 3 pages, saying basically the same stuff and even citing one another's comments to explain why you disagree with me.

Even in claiming you "weren't ganging up on me" 2 people said that same thing within 3 mins of each other lmfao. The thread was very active with all of us contributing very quickly, so I felt compelled to keep it going, which isn't your fault at all, but also added to the pressure. You guys are great, and I enjoy reading what you write. I just needed to say what happened specifically

 

[Cmaier]

Even in claiming you "weren't ganging up on me" 2 people said that same thing within 3 mins of each other lmfao.

That’s a bit of a weird thing to mention. If you said “you four each molested my cat,” the fact that each of us says “no we didn’t” within a few minutes of each other is not proof of anything, either.

 

[RockRock8]

...

Uhmmmmm okay. This conversation getting a little strange to me. Like on multiple levels. I'm sorry to have upset you in previous days, apparently, but at this point I'm not really sure what I did that warranted it or why you're acting like this or even just said that. This entire thread is pretty out of character for you. I'm going to end my part of this thread here. Sorry to have upset you.

 

[Cmaier]

Uhmmmmm okay. This conversation getting a little strange to me. Like on multiple levels. I'm sorry to have upset you in previous days, apparently, but at this point I'm not really sure what I did that warranted it or why you're acting like this or even just said that. This entire thread is pretty out of character for you. I'm going to end my part of this thread here. Sorry to have upset you.

? I’m not upset at all. Not one bit. I simply disagree with a premise of yours.

 

[casperes1996]

Agreed! But this line of logic is why I thought they wouldn't go with a Middle Core and they did! I'm not saying my "thread scheduling change to take advantage of the new core type" hypothesis is right either btw, I'm also a fan of the "un-core efficiency improvements" hypothesis. But the former is possible.

Absolutely. I wouldn’t rule it out either. Just have no expectations of changes there given current knowledge and evidence. But definitely possible

 

[RockRock8]

? I’m not upset at all. Not one bit. I simply disagree with a premise of yours.

You just reworded my feedback and equated to claiming you guys did that, which I really struggle to understand why you picked that as a metaphor, it didn't even need a metaphor or analogy. You're either upset or aren't thinking your own responses back to me through enough. I don't appreciate it either way.

I didn't accuse you of that. I literally just asked -- lighthearted in intention, if not execution -- to stop piling on. You guys were doing that, and then when called out you piled on again in denial within minutes of each other. Do you see why changing the feedback to something as weird and irrelevant as what you said is not only inappropriate, but counter productive to the entire point of this specific feedback? I wasn't even looking for an apology, good god

 

[Cmaier]

You just reworded my feedback and equated to claiming you guys did that, which I really struggle to understand why you picked that as a metaphor, it didn't even need a metaphor or analogy. You're either upset or aren't thinking your own responses back to me through enough. I don't appreciate it either way.

I didn't accuse you of that. I literally just asked -- lighthearted in intention, if not execution -- to stop piling on. You guys were doing that, and then when called out you piled on again in denial within minutes of each other. Do you see why changing the feedback to something as weird and irrelevant as what you said is not only inappropriate, but counter productive to the entire point of this specific feedback? I wasn't even looking for an apology, good god

I know you didn’t accuse us of that. I was making an argument by way of analogy, a common rhetorical technique.

 

[mr_roboto]

Could the M5 Pro and Max already be on N2? It has been in production for several months.

Apple's press page says "two third-generation 3-nanometer dies".

Usually the first few months of a new node are risk production - yields may be low, wafer throughput definitely low-ish.

From my sources, I believe the CPU cores are all on the same die, and the GPU is on the other die.

An interesting question (to me, anyways) is where the memory controllers live. You'd like them to be on the same die as the CPUs to minimize latency, but on the same die as the GPUs to scale memory controller count / bandwidth with GPU core count.

My guess is CPU + media engine + IO on one die, MCs + GPU on another, and the MC+GPU die has two shorelines (north and south) dedicated to die-to-die interconnect. (Allowing construction of an Ultra with two GPU die surrounded by two CPU die endcaps.)

 

[leman]

An interesting question (to me, anyways) is where the memory controllers live. You'd like them to be on the same die as the CPUs to minimize latency, but on the same die as the GPUs to scale memory controller count / bandwidth with GPU core count.

My guess is CPU + media engine + IO on one die, MCs + GPU on another, and the MC+GPU die has two shorelines (north and south) dedicated to die-to-die interconnect. (Allowing construction of an Ultra with two GPU die surrounded by two CPU die endcaps.)

My guess is the same. What's more, due to how Apple's memory hierarchy work, the memory controllers will very likely be close to the SLC cache. It would ever interesting to see whether the memory access latency has changed for the CPU. I am also curious on whether it's 2D die arrangement or a 2.5D/3D.

 

[Nycturne]

I'm not really a fan of the term "super" core. Do we get "hyper" cores in a few years then?
I can understand that they want to distinguish between high-performance, more efficent performance, and efficency cores, but still...

Us in 2030: "They've gone to plaid!"

Also, this architecture looks similar to current Intel CPUs: A handfull performance cores, with a dozen more efficient cores.
But knowing Apple, I'm guessing that both the efficency and the "medium" performance cores are likely better than Intel's efficency cores (are they still directly derived from Atom cores as in the beginning?).

I've harped on this before, but Intel's approach is mostly kneecapped (IMO) by the fact that the scheduler Intel uses tries to leverage the efficiency cores for user-interactive stuff to keep the system from turbo-boosting into oblivion. So you get this weird setup where certain tasks will shift back and forth depending on if the scheduler thinks the thread will benefit from it. End result is that your performance is a little less deterministic than you might expect. Apple's approach is deterministic, and because of their overall efficiency, they can favor speed for user-interactive tasks.

It doesn't upset me. It perplexes me. I'm so confused that this thread is more upset about names than hyped about the performance lol. I mean I understand talking about it, but that's like the narrative of the whole thread

The "super" cores are the same as what we got in the fall. So, not much new there to get excited about. We can already guess there's a bit of a ST uplift over M5, but it's going to be similar to the uplift between base M4 and M4 Pro/Max in the MacBook Pros. These new middle ground cores are new, and interesting, but there's not as much meat to gnaw on off a press release. Not yet. Same with the chiplet fusion they are doing. What are you expecting to analyze here?

30% MT uplift over the M4 Pro/Max is good.

Possibly. I'm just not really sure the desired characteristics of changing the scheduling behaviour.
If something is explicitly labelled to be background work that isn't time sensitive, put it on the most efficient core we have, no-brainer. If all we have is background-tier jobs, clock-gate that cluster too.
Any work that may affect the responsiveness of the system or how quickly a task the user may be waiting on finishes, schedule on S cores first, and if there's so many parallel threads not yielding the CPU that we can spill the task Into the P cores, do that.

Agreed with everything you said here, and I'd just add that simple, deterministic behaviors in a scheduler is a benefit. It allows developers to make better choices about how they tag work for the scheduler. Complexity just adds more things to track and get right.

 

[leman]

Explain to me why you think it's the N1 chip contributing most of the battery life increase and not the new chip, despite the fact that the MBA has the N1 chip and doesn't have any battery increase at all. I'm not the expert.

I don't know if it's the N1 chip contributing or something else (your point about M1 having the same chip and not experiencing an increase is a good one). My point is that I don't see how the changes to the CPU clusters could have resulted in significant power saving, unless they are also accompanied by a new, more efficient on-chip network and improvements to other IP blocks (=uncore) that drive these improvements.