I don't think that would work. The physical size of the gates is different. So either there wouldn't be room for your gates in the performance variation (impossible design), or there'd be wasted space in the efficiency variation (space-inefficient design). Neither outcome is desirable.
I don’t even understand the proposal. These are standard cell designs, largely. For any given logic cell, there are multiple variations, each corresponding to a different effective strength. For a two input nand gate, you have nand2x1, nand2x2, nand2x4, etc. As the number after the x increases, so, too, does the physical size of the gate, the power consumed by the gate when it switches, and, all
Else equal, the speed of switching the gate.
This has always been the case - in the old days it was done by drawing transistors with bigger width-to-length ratio. Now it is done by using more and/or bigger fins.
It has always been the case that a core will use a mixture of all these different strengths, depending on the needs of a given logic path.
When I started at Exponential Technology, they were taping out their first chip, and they ran their design through a tool they developed called “Hoover.” This tool went path by path and reduced the size of gates that it thought could be shrunk in order to reduce power consumption while still meeting timing constraints. I think the samples arrived shortly after I joined. Instead of running at 533mhz, as designed, the he chip ran at 420mhz.
One of my first tasks was to figure out why, and I recall us printing out a giant schematic and me doing the Roth-d algorithm on it in pencil with a colleague to try and find a set of test inputs to figure out what went wrong.
Turns out Hoover didn’t account for cross coupling, so by making so many weak driving gates, wires were being heavily jerked around by signal changes on their neighbors, and which cost 20 percent of the chip’s performance. This became a subject of the article I wrote for IEEE Journal of Solid State Circuits about the chip, where I derived that the maximum relationship between gate sizes that you should have on two neighboring wires.
Anyway, not really relevant, but a fun story about “gate sizing.”
The real point is that it is already the case and has always been the case that the effective size of transistors in a core always differs from place to place, and doing it by fin count or fin size doesn’t really make too much difference.
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