M5 Pro and Max unveiled

[dada_dave]

Yeah I guess I’m put off by the headline that the Max showed little improvement when what they mean is the 14” shows little improvement when compared to the 16” M4 Max

Fair, the one note of concern though is that the 16" Pro has the same CPU but with cut down memory bandwidth as the M5 Max and for some reason it's slower than the 14" M5 Max and is less efficient as well! Every previous time I've gone with the "it's the memory bandwidth" hypothesis to explain odd CB 24 results, I've usually, eventually, come to the conclusion that it wasn't. But here ... again, I don't know how else to explain this even though, as CPU bandwidth goes, the M5 Pro has a ton! (Not sure how much it can access admittedly) I mean, workstation CPU level bandwidth. So I dunno what's going on.

So it can't just be the 14"'s lack of cooling.

From @JRLMustang: https://arstechnica.com/gadgets/202...ook-pro-m5-max-and-its-new-performance-cores/



The M5 6-E-core cluster has 6MB of cache while there are a 2 clusters of 6 "P-"cores each with 8MB of cache and the 6-"S-"core cluster has 16MB.

This Ars article has the M5 Max CB 2024 result at 2300. Why the M5 Pro with the same CPU only gets ~2050 while drawing >100W (basically matching the M4 Max with much higher power draw) is ... unclear to put it mildly.

More Cyberpunk benchmarks. The lack of increase in some scores is weird. Again from Hardware Canucks
View attachment 38321

This Warhammer 3: Total War shows a similar lack of improvement.
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I dunno ... driver issues?

 

[Jimmyjames]

This Ars article has the M5 Max CB 2024 result at 2300. Why the M5 Pro with the same CPU only gets ~2050 while drawing >100W (basically matching the M4 Max with much higher power draw) is ... unclear to put it mildly.



I dunno ... driver issues?

Yeah could be. Or just a lack of optimisation overall?

 

[MerryCherry]

The M5 6-E-core cluster has 6MB of cache while there are a 2 clusters of 6 "P-"cores each with 8MB of cache and the 6-"S-"core cluster has 16MB.

So no 1 MB private L2 like some rumour mongers were saying?

It's interesting how M5 Pro/Max are getting by with relatively less cache compared to the competition.

SoC	L2	L3	Total CPU cache
Apple M5 Max	16 MB + 8 MB + 8 MB	-	32 MB
AMD Strix Halo	1 MB x16	64 MB	80 MB
Qualcom X2 Elite Extreme	16 MB + 16 MB + 12 MB		44 MB
Intel Core Ultra 388H	(3 MB x4) + (4 MB x3)	18 MB	42 MB

 

[Jimmyjames]

From X unfortunately but here is a test Max Weinbach did comparing a mobile 5080 on power vs M5 Max on battery. All settings maximum accept path tracing. 5080M 27 fps, M5 Max 23 fps.

With path tracing it’s 17 fps for the 5080 vs 13 fps for the M5 Max

There is a video on X of this test.

 

[exoticspice1]

This Ars article has the M5 Max CB 2024 result at 2300. Why the M5 Pro with the same CPU only gets ~2050 while drawing >100W (basically matching the M4 Max with much higher power draw) is ... unclear to put it mildly.

I'll test CB2024 when I get my M5 Pro for testing tomorrow. But Cinebench 2026 is fine as per CNET testing.

 

[dada_dave]

So no 1 MB private L2 like some rumour mongers were saying?

It's possible its a misunderstanding based on what @leman was saying that each core has a slice of L2 that isn't exactly private but is also considered "for that core", just that other cores can also see it ... unless I also misunderstood what he was saying.

It's interesting how M5 Pro/Max are getting by with relatively less cache compared to the competition.

SoC	L2	L3	Total CPU cache
Apple M5 Max	16 MB + 8 MB + 8 MB	-	32 MB
AMD Strix Halo	1 MB x16	64 MB	80 MB
Qualcom X2 Elite Extreme	16 MB + 16 MB + 12 MB		44 MB
Intel Core Ultra 388H	(3 MB x4) + (4 MB x3)	18 MB	42 MB

Don't forget that Apple and Qualcomm also have SLCs which function like an L3 - although their L2 also sort of functions like an L3 since it is per cluster rather than per core. Very different cache philosophy - partly because Apple's L1 is so big. Intel also has "L1.5" - which I think really is L1, or maybe I screwed that up, but I remember them adding another layer. .

 

[mr_roboto]

Don't forget that Apple and Qualcomm also have SLCs which function like an L3 - although their L2 also sort of functions like an L3 since it is per cluster rather than per core. Very different cache philosophy - partly because Apple's L1 is so big. Intel also has "L1.5" - which I think really is L1, or maybe I screwed that up, but I remember them adding another layer. .

IIRC they just added another layer, but marketing renamed L1 to L0 so they could claim they had a big L1. Or something like that.

Along similar lines... According to Ars Technica, powermetrics reports the "Performance" core clusters in M5 Pro/Max as M0 and M1, and the "Super" cluster as P0. I take this as confirmation that the "Super" rebranding nonsense is just confusion created by marketing weenies who were afraid to describe the new core type as "Mid" or "Medium" (or whatever it was engineering had in mind when designating them as M0 and M1).

 

[dada_dave]

IIRC they just added another layer, but marketing renamed L1 to L0 so they could claim they had a big L1. Or something like that.

Along similar lines... According to Ars Technica, powermetrics reports the "Performance" core clusters in M5 Pro/Max as M0 and M1, and the "Super" cluster as P0. I take this as confirmation that the "Super" rebranding nonsense is just confusion created by marketing weenies who were afraid to describe the new core type as "Mid" or "Medium" (or whatever it was engineering had in mind when designating them as M0 and M1).

Re: P and M, yeah I noticed that too

I think you’re correct about Intel’s cache change as well, I think we even had this conversation before

 

[Cmaier]

IIRC they just added another layer, but marketing renamed L1 to L0 so they could claim they had a big L1. Or something like that.

Along similar lines... According to Ars Technica, powermetrics reports the "Performance" core clusters in M5 Pro/Max as M0 and M1, and the "Super" cluster as P0. I take this as confirmation that the "Super" rebranding nonsense is just confusion created by marketing weenies who were afraid to describe the new core type as "Mid" or "Medium" (or whatever it was engineering had in mind when designating them as M0 and M1).

Don’t know what Intel does, but frequently “L0” refers to a cache that is different-in-kind from the other layers, for example caching µops instead of instructions.

 

[dada_dave]

Don’t know what Intel does, but frequently “L0” refers to a cache that is different-in-kind from the other layers, for example caching µops instead of instructions.

I think in this case Intel renamed L1 L0 and added a new L1 cache that was really an L1.5, basically a second faster L2. So it was really L1, L1.5, L2, L3 but they called it L0, L1, L2, L3.

 

[dada_dave]

From the NBC article on the M5 Pro. Now I'm pretty sure the above are powermetrics readings rather than wall power. But I don't think you can get from these to >100W of wall power on the CPU under CB 24, especially not when they have the wall power of the thermally constrained M5 Max, which is the same CPU, getting the same score drawing only 85W of wall power. We'll see what happens when they drop the M5 Max review, but something has to be wrong about the M5 Pro efficiency scores.