M5 Pro and Max unveiled

[Nycturne]

My understanding is, as far as the operating system is concerned, the “S” cores are named “P,” and the “P” cores are named “E.”

Having been in the field as long as I have, I will never underestimate the silly things someone will do to try to identify something, leaning on user-facing naming when they shouldn't/etc. Trying to parse the output of `system_profiler SPHardwareDataType` or something equally silly would probably not do what someone expects with the renaming in M5.

Now, I'm not claiming this is exactly what Logic did, I'm just presenting a possibility that happens to fit the seen behaviors.

EDIT: Although now I'm curious what sysctl hw.perflevel0/1 return on an M5 Pro/Max.

 

[Cmaier]

I thought the P cores were named "M"?

Not inside the OS, which apparently only supports the P and E designations at this point.

 

[dada_dave]

Not inside the OS, which apparently only supports the P and E designations at this point.

So they're then hardcoding powermetrics to say "M" instead of "E"?

Having been in the field as long as I have, I will never underestimate the silly things someone will do to try to identify something, leaning on user-facing naming when they shouldn't/etc. Trying to parse the output of `system_profiler SPHardwareDataType` or something equally silly would probably not do what someone expects with the renaming in M5.

Now, I'm not claiming this is exactly what Logic did, I'm just presenting a possibility that happens to fit the seen behaviors.

EDIT: Although now I'm curious what sysctl hw.perflevel0/1 return on an M5 Pro/Max.

I believe it returns "P0" and "M0/1"

Edit sorry was thinking of powermetrics output, the arstechnica article linked to earlier in the thread mentions running sysctl but not what the names used there were

 

[leman]

EDIT: Although now I'm curious what sysctl hw.perflevel0/1 return on an M5 Pro/Max.

I bet my left pinky toe that the numbers are going to be 12 and 6.

 

[Jimmyjames]

Wow. The M5 Max took a big jump on Blender 5.1. Some others did too, but some didn’t. Now the Max is faster than the desktop 5070 ti, the M3 Ultra (80 core).

 

[Jimmyjames]

Not sure if anyone’s interested but..

 

[Jimmyjames]

Posting Blender data until I get banned!

Here are the individual Blender 5.1.0 scores with each subtest score listed for the M5 Max and the 5090 Laptop. Monster is the simplest test and Classroom the most complex. We can see the M5 Max does better in more complex scenes. Boding well for real life work.

 

[Jimmyjames]

Interview in German (I used Safari to translate) with Apple employees, including Anand! The topic is the new Performance core, the new Fusion architecture and a couple of other things..

https://archive.ph/kDE0u

 

[NotEntirelyConfused]

Interview in German (I used Safari to translate) with Apple employees, including Anand! The topic is the new Performance core, the new Fusion architecture and a couple of other things..

https://archive.ph/kDE0u

In a translation of that article, he is quoted as saying that the chiplets in the M5 are *stacked*. Surely not! ISTM that any performance/power wins you'd get from stacking a CPU and GPU chiplet would be lost to increased heat density. Well, performance anyway - power maybe not. But given that they've been spending some efficiency to raise performance, that would seem like an unlikely course for them to take. My guess is that they're both stacked on a substrate, and that's what me meant. But no way to know for sure until we see die shots. Or, well, maybe, a heat image.

 

[leman]

In a translation of that article, he is quoted as saying that the chiplets in the M5 are *stacked*. Surely not! ISTM that any performance/power wins you'd get from stacking a CPU and GPU chiplet would be lost to increased heat density. Well, performance anyway - power maybe not. But given that they've been spending some efficiency to raise performance, that would seem like an unlikely course for them to take. My guess is that they're both stacked on a substrate, and that's what me meant. But no way to know for sure until we see die shots. Or, well, maybe, a heat image.

I don't see any reference to stacking in the linked German text. Is there maybe an interview transcript that I have missed?I don't have a Heise subscription, so I can't read the stuff on the actual website. Apple does have a patent for combining two heterogeneous dies into a single SoC that uses stacking — but in that patent the dies only partially overlap. The way I understand it the goal is area reduction first and foremost.

P.S. @Cmeier is much more attentive than me! Yes, it is mentioned in the text.

 

[Cmaier]

In a translation of that article, he is quoted as saying that the chiplets in the M5 are *stacked*. Surely not! ISTM that any performance/power wins you'd get from stacking a CPU and GPU chiplet would be lost to increased heat density. Well, performance anyway - power maybe not. But given that they've been spending some efficiency to raise performance, that would seem like an unlikely course for them to take. My guess is that they're both stacked on a substrate, and that's what me meant. But no way to know for sure until we see die shots. Or, well, maybe, a heat image.

Hmm, maybe this?

Beim M5 Pro und M5 Max kommt eine neue Fusion-Architektur zum Einsatz, die zwei übereinanderliegende Dies (das sind die aus Silizium bestehenden Trägerplatten für die Transistoren) verbindet.

It means something like:

The M5 Pro and M5 Max use a new fusion architecture that connects two superimposed dies (these are carrier plates for the transistors made of silicon).

The adjective übereinanderliegende definitely implies that they overlap vertically, though I’ll defer to our native speakers.

Maybe they thinned the die substrates substantially so they can take heat out the back. I dunno.

 

[TommyYOyoyo]

Has anybody measured the Powermetrics stable "combined Power" reading during Cinebench 2026 CPU multi-core load for M5 Pro?

 

[leman]

Hmm, maybe this?

Beim M5 Pro und M5 Max kommt eine neue Fusion-Architektur zum Einsatz, die zwei übereinanderliegende Dies (das sind die aus Silizium bestehenden Trägerplatten für die Transistoren) verbindet.

It means something like:

The M5 Pro and M5 Max use a new fusion architecture that connects two superimposed dies (these are carrier plates for the transistors made of silicon).

The adjective übereinanderliegende definitely implies that they overlap vertically, though I’ll defer to our native speakers.

Maybe they thinned the die substrates substantially so they can take heat out the back. I dunno.

You are right, I missed that part! Nice lawyering!

Than it could indeed be this patent: https://patentscope.wipo.int/search/en/detail.jsf?docId=US470604314

 

[Cmaier]

You are right, I missed that part! Nice lawyering!

Than it could indeed be this patent: https://patentscope.wipo.int/search/en/detail.jsf?docId=US470604314

Looks pretty similar to the A-series - I spent a lot of time looking at package cross-sections for a legal case. Other than 110 and 120 in the figure on the front page, of course.

 

[leman]

Looks pretty similar to the A-series - I spent a lot of time looking at package cross-sections for a legal case. Other than 110 and 120 in the figure on the front page, of course.

A-series mounts RAM on top though, right? I think the innovation here is that you get a version of die stacking without the complex TSVs through an active die.

 

[Cmaier]

A-series mounts RAM on top though, right? I think the innovation here is that you get a version of die stacking without the complex TSVs through an active die.

yes, A-series have the RAM die above, SoC in the middle, and if i remember correctly MOS capacitors on the bottom.

 

[dada_dave]

Has anybody measured the Powermetrics stable "combined Power" reading during Cinebench 2026 CPU multi-core load for M5 Pro?

Welcome!

Notebookcheck measured it under CBR24 (not 26) but imply that was typical under multicore loads involving just the CPU:

Apple MacBook Pro 16 2026 Review - M5 Pro makes one of the best multimedia laptops even better

The MacBook Pro 16 with the M5 Pro gets a big bump both in terms of CPU as well as GPU performance. Apple also includes faster PCIe 5.0 SSDs as well as Wi-Fi 7, so the overall package is even better than before. Update: Temporal dithering test

www.notebookcheck.net

 

[JRLMustang]

Apologies if it’s already been posted (I might have missed it)

“Apple explains why M5 chips have three different core types in new interview”

Apple explains why M5 chips have three different core types in new interview - 9to5Mac

Apple explains M5's three core types: super cores for single-thread tasks, performance cores for multi-threading, and efficiency cores.

9to5mac.com

 

[TommyYOyoyo]

Hmm, according to many analysis and discussions, Apple Powermetrics almost certainly underestimates the power consumption of the SoC package on macs. It seems that the "PHPC" or "PHPS" sensors readable through apps like Stats by Exelban reflect much more accurately the total Package power consumption of M5 Pro macs, with the only caveat being needing to substract DRAM module power from it (readable through mactop)

Can anybody read what the "PHPC" or "PHPS" sensors report using Stats app in Cinebench 2026 multi-core benchmark when power stabilizes? Thanks!

 

[dada_dave]

Hmm, according to many analysis and discussions, Apple Powermetrics almost certainly underestimates the power consumption of the SoC package on macs. It seems that the "PHPC" or "PHPS" sensors readable through apps like Stats by Exelban reflect much more accurately the total Package power consumption of M5 Pro macs, with the only caveat being needing to substract DRAM module power from it (readable through mactop)

Can anybody read what the "PHPC" or "PHPS" sensors report using Stats app in Cinebench 2026 multi-core benchmark when power stabilizes? Thanks!

I’ve never used that program and I am unfamiliar with attempts to use it or those sensors to do performance efficiency. Powermetrics is indeed an estimate of just the core power itself and Apple states should only be used for assessing power usage during app development and not comparing processors.

For doing the latter, I just use data generated by NBC which reports the wall power of CB24 load & idle when connected to an external monitor, though of course that counts much more than just the CPU.