If you put that sort of flash management logic in an OS-level driver, how do you ever load the OS? At that point it can only work for extra storage and not the boot medium, right? Or you need some kind of über dumb "read this byte from this address to initialise always" ala MBR boot partitions in style and no wear levelling or any sort of flash memory management aside from that baked into the BIOS or something similar, right? Perhaps a UEFI driver could work here but it would again need to be embedded pre-flash on a ROM or something
Well... what's the boot medium? That gets a bit murky and I'll try to illustrate why with the Apple Silicon boot process. Here are its bootloader stages, and where they're stored:
Stage 0: Boot ROM - Stored in mask ROM in the SoC
Stage 1: "Low Level Boot" - Stored in unmanaged NOR flash
Stage 2: "iBoot" - Stored in managed NAND flash (AKA the boot SSD)
"stage 3": The XNU kernel - Stored in the SSD
Stage 0 is very simple. It's the root of trust in their secure boot scheme, and mask ROM is both small and read-only. There's not enough space for complex software, and even if there was, they wouldn't take advantage of it. Complexity increases the risk of bugs, and they must live with any bugs in this ROM forever.
That's why they picked low density NOR flash to store stage 1. As long as you don't write to it a lot, NOR doesn't need management because it's far less dense and far more inherently reliable than NAND flash. Besides stage 1, NOR contains firmware images for every Apple Silicon subsystem which must be brought up to make it possible to load and run stage 2. So, this is where NAND flash management starts up in Apple platforms - stage 1 reads a firmware image stored in NOR, points the SSD management CPU at it, and releases it from reset. After the SSD firmware finishes initializing, there's a live NVMe device that stage 1 (and subsequent software) can use to access the SSD's contents.
Other arrangements are possible! If Apple didn't want to hide NAND flash management from the application processors, they wouldn't need different external hardware. Fold NAND flash management into stage 1's code, and Bob's your uncle. Doesn't even have to be the same exact code as the eventual XNU flash management driver, as long as both agree on the data structures stored in the raw flash.
Another possibility is what we did in a chip I once worked on. It needed to boot Linux with a minimum of external components - so, no separate NOR flash firmware chip, only one NAND. This meant baking some very basic flash management into the mask ROM and hardware (we had a hardware engine for the BCH error correction, or whatever algorithm it was - don't remember exactly). I wasn't directly involved so I don't know or remember all the details, but I'm sure it was something along the lines of "the chip knows how to read a fixed size bootstrap program from a fixed address in flash, so that's where you put your stage 1 bootloader. Don't update it often or you'll wear out that location in flash and brick the device." Stage 1 could then contain software for more sophisticated wear-levelled management of the rest of the flash.